Hi,
On 21-09-15 14:19, Ian Campbell wrote:
On Mon, 2015-09-21 at 13:24 +0200, Hans de Goede wrote:
Hi,
On 21-09-15 12:22, Ian Campbell wrote:
On Sun, 2015-09-20 at 15:39 -0400, Hans de Goede wrote:
We know when u-boot is written to its own partition, in this case the
layout always is:
eb 0 spl
eb 1 spl-backup
eb 2 u-boot
eb 3 u-boot-backup
eb: erase-block
So if we cannot load u-boot from its primary offset we know exactly
where
to look for it.
Is it worth noting here (or perhaps in a code comment?) that the code
currently assumes that the first four ebs are of uniform size?
The eraseblock size is a property of the nand, given a certain nand chip,
all eraseblocks on that chip always have the same size.
So they never have "boot erase zones" at either the start or end, which
divide one of the erase zones into more fine-grained sizes?
e.g. it used to be the case with NOR that with, say, a 128KB device you
would have zones of 3x32K, 1x16K, 2x8K or something like that rather than
simply 4x32K.
They don't do this with NAND then?
To the best of my knowledge no.
Regards,
Hans
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