On 08/17/2015 03:31 PM, York Sun wrote: > MPC85xx has been using locked L1 cache as init_ram. L1 cache is a write > through cache on E6500. L2 cache is enabled to to hold the data. This > patch locks/unlocks L2 cache to ensure no data cast out from L2 cache. > > Signed-off-by: York Sun <york...@freescale.com> > Reported-by: Jeffery Zhu <jefferry....@freescale.com> > > ---
Applied to u-boot-mpc85xx master. Awaiting upstream. York _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
