> -----Original Message-----
> From: u-boot-boun...@lists.denx.de
> [mailto:u-boot-boun...@lists.denx.de] On Behalf Of Wolfgang Denk
> Sent: Tuesday, July 21, 2009 6:56 PM
> To: Aggrwal Poonam-B10812
> Cc: u-boot@lists.denx.de
> Subject: Re: [U-Boot] [PATCH 2/2] P2020RDB Platform Support Added
>
> Dear Poonam Aggrwal,
>
> In message
> <1248173285-30560-1-git-send-email-poonam.aggr...@freescale.co
> m> you wrote:
> > The code base is generic to add more P1_P2 RDB platforms
> support as and when required.
> > The folder and file names are such that they can cater to
> future SOCs of P1/P2 family.
> >
> > Tested the following on P2020RDB:
> > 1. eTSECs(1/2/3)
> > 2. DDR, NAND, NOR, I2C etc
> >
> > Signed-off-by: Poonam Aggrwal <poonam.aggr...@freescale.com>
> > ---
> > MAINTAINERS | 4 +
> > MAKEALL | 1 +
> > Makefile | 8 +
> > board/freescale/p1_p2_rdb/Makefile | 53 +++
> > board/freescale/p1_p2_rdb/config.mk | 32 ++
> > board/freescale/p1_p2_rdb/ddr.c | 188 ++++++++++
> > board/freescale/p1_p2_rdb/law.c | 37 ++
> > board/freescale/p1_p2_rdb/p1_p2_rdb.c | 234 ++++++++++++
> > board/freescale/p1_p2_rdb/pci.c | 174 +++++++++
> > board/freescale/p1_p2_rdb/tlb.c | 79 +++++
> > board/freescale/p1_p2_rdb/u-boot.lds | 143 ++++++++
> > doc/README.p2020rdb | 143 ++++++++
> > include/configs/P1_P2_RDB.h | 625
> +++++++++++++++++++++++++++++++++
> > 13 files changed, 1721 insertions(+), 0 deletions(-) create mode
> > 100644 board/freescale/p1_p2_rdb/Makefile
> > create mode 100644 board/freescale/p1_p2_rdb/config.mk
> > create mode 100644 board/freescale/p1_p2_rdb/ddr.c create mode
> > 100644 board/freescale/p1_p2_rdb/law.c create mode 100644
> > board/freescale/p1_p2_rdb/p1_p2_rdb.c
> > create mode 100644 board/freescale/p1_p2_rdb/pci.c create mode
> > 100644 board/freescale/p1_p2_rdb/tlb.c create mode 100644
> > board/freescale/p1_p2_rdb/u-boot.lds
> > create mode 100644 doc/README.p2020rdb create mode 100644
> > include/configs/P1_P2_RDB.h
> >
> > diff --git a/MAINTAINERS b/MAINTAINERS index 705bac5..814912c 100644
> > --- a/MAINTAINERS
> > +++ b/MAINTAINERS
> > @@ -436,6 +436,10 @@ Peter Tyser <pty...@xes-inc.com>
> > XPEDITE5200 MPC8548
> > XPEDITE5370 MPC8572
> >
> > +Poonam Aggrwal <poonam.aggr...@freescale.com>
> > +
> > + P2020RDB P2020
> > +
> > David Updegraff <d...@cray.com>
>
> Please keep list sorted by names.
>
> > diff --git a/Makefile b/Makefile
> > index 2a06440..dc3e987 100644
> > --- a/Makefile
> > +++ b/Makefile
> > @@ -1,4 +1,5 @@
> > #
> > +# Copyright (C) 2009 Freescale Semiconductor, Inc. All
> rights reserved.
>
> Please note that
>
> 1) I don't think that you have any real right to add a (C) note to
> this file for just adding anothe rboard entry.
>
> 2) Your copyright note, especially the phrase "All rights reserved."
> is incompatible with the GPL.
>
> We cannot accept any such code. Plase make sure never to
> use that in
> any submissions to this project, as we can then only relect your
> code.
I will rework the copyright stuff.
>
> > diff --git a/board/freescale/p1_p2_rdb/ddr.c
> > b/board/freescale/p1_p2_rdb/ddr.c new file mode 100644 index
> > 0000000..2b880ab
> > --- /dev/null
> > +++ b/board/freescale/p1_p2_rdb/ddr.c
> > @@ -0,0 +1,188 @@
> > +/*
> > + * Copyright (C) 2009 Freescale Semiconductor, Inc. All
> rights reserved.
> > + *
> > + * See file CREDITS for list of people who contributed to this
> > + * project.
> > + *
> > + * This program is free software; you can redistribute it and/or
> > + * modify it under the terms of the GNU General Public License as
> > + * published by the Free Software Foundation; either version 2 of
> > + * the License, or (at your option) any later version.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> > + * GNU General Public License for more details.
> > + *
> > + * You should have received a copy of the GNU General
> Public License
> > + * along with this program; if not, write to the Free Software
> > + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> > + * MA 02111-1307 USA
> > + */
> > +
> > +#include <common.h>
> > +#include <asm/mmu.h>
> > +#include <asm/immap_85xx.h>
> > +#include <asm/fsl_ddr_sdram.h>
> > +#include <asm/io.h>
> > +#include <asm/fsl_law.h>
> > +
> > +
> > +#if defined(CONFIG_DDR_ECC) &&
> > +!defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
> > +extern void ddr_enable_ecc(unsigned int dram_size); #endif
> > +
> > +phys_size_t fixed_sdram(void);
> > +
> > +unsigned long get_board_ddr_size(ulong dummy) {
> > + return 1024;
> > +}
>
> Please use auto-detection of the memory size (using get_ram_size()).
Thanks for the suggestion, I was not aware of this function.
>
> > + u32 val, temp;
> > + volatile ccsr_gpio_t *pgpio = (void
> *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
> > + char board_rev = 0;
> > + struct cpu_type *cpu;
> > +
> > + val = pgpio->gpdat;
> > + temp = val & BOARDREV_MASK;
> > + if (temp == BOARDREV_C)
> > + board_rev = 'C';
> > + else if (temp == BOARDREV_B)
> > + board_rev = 'B';
>
> What happens if it's neither BOARDREV_B nore BOARDREV_C ?
It has to be rev b or revC , may be we can spin here.
>
> > > +}
> > +#endif
> > +
> > +/*
> > + * Miscellaneous late-boot configurations
> > + *
> > + * If a VSC7385 microcode image is present, then upload it.
> > +*/
> > +int misc_init_r(void)
> > +{
> > + int rc = 0;
> > +
> > +
> > +#ifdef CONFIG_VSC7385_IMAGE
> > + printf(" uploading VSC7385 microcode.from %x\n",
> > +CONFIG_VSC7385_IMAGE);
>
> Please check alignment of the output.
>
> Why don't you use an environment variable for the image address?
Thanks for the sugggestion, I will do that.
>
> > diff --git a/include/configs/P1_P2_RDB.h
> b/include/configs/P1_P2_RDB.h
> > new file mode 100644 index 0000000..99f62f6
> > --- /dev/null
> > +++ b/include/configs/P1_P2_RDB.h
> ...
> > +/*
> > +/* These are used when DDR doesn't use SPD. */
> > +/* DDR2 at 533MHz, 512MB */
> > +#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F
> > +#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202 /*
> Enable, no interleaving */
> > +#define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
> > +
> > +#define CONFIG_SYS_DDR_TIMING_3_533 0x00020000
> > +#define CONFIG_SYS_DDR_TIMING_0_533 0x00260802
> > +#define CONFIG_SYS_DDR_TIMING_1_533 0x4c47c432
> > +#define CONFIG_SYS_DDR_TIMING_2_533 0x0f9848ce
> > +#define CONFIG_SYS_DDR_TIMING_4_533 0x00000000
> > +#define CONFIG_SYS_DDR_TIMING_5_533 0x00000000
> > +#define CONFIG_SYS_DDR_CLK_CTRL_533 0x02800000
> > +#define CONFIG_SYS_DDR_MODE_1_533 0x00040642
> > +#define CONFIG_SYS_DDR_MODE_2_533 0x00000000
> > +#define CONFIG_SYS_DDR_INTERVAL_533 0x08200100
> > +#define CONFIG_SYS_DDR_CONTROL_533 0x43000000
> /* Type = DDR2 */
> > +#define CONFIG_SYS_DDR_CONTROL2_533 0x24401000
> > +
> > +
> > +#define CONFIG_SYS_DDR_TIMING_3_400 0x00010000
> > +#define CONFIG_SYS_DDR_TIMING_0_400 0x00260802
> > +#define CONFIG_SYS_DDR_TIMING_1_400 0x39355322
> > +#define CONFIG_SYS_DDR_TIMING_2_400 0x1f9048ca
> > +#define CONFIG_SYS_DDR_TIMING_4_400 0x00000000
> > +#define CONFIG_SYS_DDR_TIMING_5_400 0x00000000
> > +#define CONFIG_SYS_DDR_CLK_CTRL_400 0x02800000
> > +#define CONFIG_SYS_DDR_MODE_1_400 0x00480432
> > +#define CONFIG_SYS_DDR_MODE_2_400 0x00000000
> > +#define CONFIG_SYS_DDR_INTERVAL_400 0x06180100
> > +#define CONFIG_SYS_DDR_CONTROL_400 0x43000000
> /* Type = DDR2 */
> > +#define CONFIG_SYS_DDR_CONTROL2_400 0x24401000
>
> How about defining a structure with these parameters, and
> then initializing an array of structs?
>
> That would significantly improve readability.
Will make the changes.
>
Regards
Poonam
> --
> DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
> Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email:
> w...@denx.de I am more bored than you could ever possibly be.
> Go back to work.
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