The p2020DS, MPC8536DS, MPC8572DS, MPC8544DS boards are capable of
swizzling the upper address bits of the NOR flash we boot out of which
creates the concept of "virtual" banks. This is useful in that we can
flash a test of image of u-boot and reset to one of the virtual banks
while still maintaining a working image in "bank 0".
The PIXIS FPGA exposes registers on LBC which we can use to determine
which "bank" we are booting out of (as well as setting which bank to
boot out of).
Signed-off-by: Kumar Gala <ga...@kernel.crashing.org>
---
* This is a merged version of previous patches that covers all the 85xx boards
board/freescale/mpc8536ds/mpc8536ds.c | 18 ++++++++++++++++--
board/freescale/mpc8544ds/mpc8544ds.c | 11 +++++++++--
board/freescale/mpc8572ds/mpc8572ds.c | 21 ++++++++++++++++++++-
board/freescale/p2020ds/p2020ds.c | 12 +++++++++++-
4 files changed, 56 insertions(+), 6 deletions(-)
diff --git a/board/freescale/mpc8536ds/mpc8536ds.c
b/board/freescale/mpc8536ds/mpc8536ds.c
index 28b27ee..91fb87b 100644
--- a/board/freescale/mpc8536ds/mpc8536ds.c
+++ b/board/freescale/mpc8536ds/mpc8536ds.c
@@ -60,10 +60,24 @@ int board_early_init_f (void)
int checkboard (void)
{
- printf ("Board: MPC8536DS, System ID: 0x%02x, "
- "System Version: 0x%02x, FPGA Version: 0x%02x\n",
+ u8 vboot;
+
+ puts("Board: MPC8536DS ");
+#ifdef CONFIG_PHYS_64BIT
+ puts("(36-bit addrmap) ");
+#endif
+
+ printf ("Sys ID: 0x%02x, "
+ "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
in8(PIXIS_BASE + PIXIS_ID), in8(PIXIS_BASE + PIXIS_VER),
in8(PIXIS_BASE + PIXIS_PVER));
+
+ vboot = in8(PIXIS_BASE + 0x16);
+ if ((vboot >> 7) & 0x1)
+ puts ("Promjet\n");
+ else
+ printf ("vBank: %d\n", ((vboot >> 5) & 0x3));
+
return 0;
}
diff --git a/board/freescale/mpc8544ds/mpc8544ds.c
b/board/freescale/mpc8544ds/mpc8544ds.c
index 34bdbad..5a199f7 100644
--- a/board/freescale/mpc8544ds/mpc8544ds.c
+++ b/board/freescale/mpc8544ds/mpc8544ds.c
@@ -43,15 +43,22 @@ int checkboard (void)
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
+ u8 vboot;
if ((uint)&gur->porpllsr != 0xe00e0000) {
printf("immap size error %lx\n",(ulong)&gur->porpllsr);
}
- printf ("Board: MPC8544DS, System ID: 0x%02x, "
- "System Version: 0x%02x, FPGA Version: 0x%02x\n",
+ printf ("Board: MPC8544DS, Sys ID: 0x%02x, "
+ "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
in8(PIXIS_BASE + PIXIS_ID), in8(PIXIS_BASE + PIXIS_VER),
in8(PIXIS_BASE + PIXIS_PVER));
+ vboot = in8(PIXIS_BASE + 0x16);
+ if ((vboot >> 7) & 0x1)
+ printf ("vBank: %d\n", ((vboot >> 6) & 0x1));
+ else
+ puts ("Promjet\n");
+
lbc->ltesr = 0xffffffff; /* Clear LBC error interrupts */
lbc->lteir = 0xffffffff; /* Enable LBC error interrupts */
ecm->eedr = 0xffffffff; /* Clear ecm errors */
diff --git a/board/freescale/mpc8572ds/mpc8572ds.c
b/board/freescale/mpc8572ds/mpc8572ds.c
index 4b95617..1d4f9bb 100644
--- a/board/freescale/mpc8572ds/mpc8572ds.c
+++ b/board/freescale/mpc8572ds/mpc8572ds.c
@@ -42,14 +42,33 @@ long int fixed_sdram(void);
int checkboard (void)
{
+ u8 vboot;
+
puts ("Board: MPC8572DS ");
#ifdef CONFIG_PHYS_64BIT
puts ("(36-bit addrmap) ");
#endif
printf ("Sys ID: 0x%02x, "
- "Sys Ver: 0x%02x, FPGA Ver: 0x%02x\n",
+ "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
in8(PIXIS_BASE + PIXIS_ID), in8(PIXIS_BASE + PIXIS_VER),
in8(PIXIS_BASE + PIXIS_PVER));
+
+ vboot = in8(PIXIS_BASE + 0x16);
+ switch (((vboot >> 6) & 0x3)) {
+ case 0:
+ puts ("vBank: 0\n");
+ break;
+ case 1:
+ puts ("Promjet\n");
+ break;
+ case 2:
+ puts ("NAND\n");
+ break;
+ case 3:
+ puts ("vBank: 1\n");
+ break;
+ }
+
return 0;
}
diff --git a/board/freescale/p2020ds/p2020ds.c
b/board/freescale/p2020ds/p2020ds.c
index 293e5a4..292a820 100644
--- a/board/freescale/p2020ds/p2020ds.c
+++ b/board/freescale/p2020ds/p2020ds.c
@@ -47,14 +47,24 @@ phys_size_t fixed_sdram(void);
int checkboard(void)
{
+ u8 sw7;
+
puts("Board: P2020DS ");
#ifdef CONFIG_PHYS_64BIT
puts("(36-bit addrmap) ");
#endif
+
printf("Sys ID: 0x%02x, "
- "Sys Ver: 0x%02x, FPGA Ver: 0x%02x\n",
+ "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
in8(PIXIS_BASE + PIXIS_ID), in8(PIXIS_BASE + PIXIS_VER),
in8(PIXIS_BASE + PIXIS_PVER));
+
+ sw7 = in8(PIXIS_BASE + 0x2c);
+ if ((sw7 >> 7) & 0x1)
+ puts ("Promjet\n");
+ else
+ printf ("vBank: %d\n", ((sw7 >> 4) & 0x3));
+
return 0;
}
--
1.6.0.6
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