Support pci uart devices in the device tree with driver model.
With this series, pci uart now works on Intel Crown Bay with driver model.
"dm tree" output below:
=> dm tree
Class Probed Name
----------------------------------------
root [ + ] root_driver
serial [ ] |-- serial
rtc [ ] |-- rtc
gpio [ ] |-- gpioa
gpio [ ] |-- gpiob
spi [ + ] |-- spi
spi_flash [ ] | `-- spi-flash@0
pci [ + ] |-- pci
pci [ + ] | |-- pcie@17,0
pci [ + ] | | `-- topcliff@0,0
serial [ ] | | |-- uart@a,1
serial [ ] | | |-- uart@a,2
serial [ + ] | | |-- uart@a,3
serial [ ] | | |-- uart@a,4
pci_generic [ ] | | |-- pci_2:0.0
pci_generic [ ] | | |-- pci_2:0.1
pci_generic [ ] | | |-- pci_2:0.2
pci_generic [ ] | | |-- pci_2:2.0
pci_generic [ ] | | |-- pci_2:2.1
pci_generic [ ] | | |-- pci_2:2.2
pci_generic [ ] | | |-- pci_2:2.3
pci_generic [ ] | | |-- pci_2:6.0
pci_generic [ ] | | |-- pci_2:8.0
pci_generic [ ] | | |-- pci_2:8.1
pci_generic [ ] | | |-- pci_2:8.2
pci_generic [ ] | | |-- pci_2:8.3
pci_generic [ ] | | |-- pci_2:a.0
pci_generic [ ] | | |-- pci_2:c.0
pci_generic [ ] | | |-- pci_2:c.2
pci_generic [ ] | | `-- pci_2:c.3
pci_generic [ ] | |-- pci_0:0.0
pci_generic [ ] | |-- pci_0:2.0
pci [ + ] | |-- pci_0:18.0
pci [ + ] | |-- pci_0:19.0
pci [ + ] | |-- pci_0:1a.0
pci_generic [ ] | |-- pci_0:1b.0
pci_generic [ ] | `-- pci_0:1f.0
simple_bus [ + ] `-- cpus
cpu [ + ] |-- cpu@0
cpu [ + ] `-- cpu@1
Changes in v4:
- Fix memory leak in device_probe_child()
Changes in v3:
- Rebase on u-boot-x86/master
- Drop v2 patches which were already applied
Bin Meng (4):
dm: pci: Optimize pci_uclass_post_bind()
dm: core: Fix code reentrancy issue in device_probe_child()
x86: crownbay: Support Topcliff integrated pci uart devices with
driver model
dm: pci: Document binding of pci device drivers
arch/x86/dts/crownbay.dts | 15 ++++++---
doc/driver-model/pci-info.txt | 71 +++++++++++++++++++++++++++++++++++++++++--
drivers/core/device.c | 19 +++++++++---
drivers/pci/pci-uclass.c | 7 +++++
4 files changed, 99 insertions(+), 13 deletions(-)
--
1.8.2.1
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