Hi Sergey, On 18 August 2015 at 06:26, Sergey Temerkhanov <s.temerkha...@gmail.com> wrote: > This commit adds basic Cavium ThunderX 88xx board definitions and support. > > Signed-off-by: Sergey Temerkhanov <s.temerkha...@gmail.com> > Signed-off-by: Radha Mohan Chintakuntla <rchintakun...@cavium.com> > > --- > > Changes in v4: > - Moved CONFIG_SYS_PROMPT to configs/thunderx_88xx_defconfig > - Add proper DM_SERIAL definitions > > Changes in v3: > - Fixed formatting > - Added MAINTAINERS > - Moved command definitions to defconfig > > Changes in v2: None > > arch/arm/Kconfig | 4 + > board/cavium/thunderx/Kconfig | 19 +++++ > board/cavium/thunderx/MAINTAINERS | 6 ++ > board/cavium/thunderx/Makefile | 8 ++ > board/cavium/thunderx/thunderx.c | 86 ++++++++++++++++++++++ > configs/thunderx_88xx_defconfig | 28 +++++++ > include/configs/thunderx_88xx.h | 149 > ++++++++++++++++++++++++++++++++++++++ > 7 files changed, 300 insertions(+) > create mode 100644 board/cavium/thunderx/Kconfig > create mode 100644 board/cavium/thunderx/MAINTAINERS > create mode 100644 board/cavium/thunderx/Makefile > create mode 100644 board/cavium/thunderx/thunderx.c > create mode 100644 configs/thunderx_88xx_defconfig > create mode 100644 include/configs/thunderx_88xx.h > > diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig > index ee9a1b3..873a9b9 100644 > --- a/arch/arm/Kconfig > +++ b/arch/arm/Kconfig > @@ -830,6 +830,9 @@ config TARGET_STM32F429_DISCOVERY > bool "Support STM32F429 Discovery" > select CPU_V7M > > +config TARGET_THUNDERX_88XX > + bool "Support ThunderX 88xx"
Can you please add help here, spending 4-5 lines describing the board in rough terms. As an example, see arch/x86/Kconfig: config TARGET_CHROMEBOOK_LINK bool "Support Chromebook link" help This is the Chromebook Pixel released in 2013. It uses an Intel i5 Ivybridge which is a die-shrink of Sandybridge, with 4GB of SDRAM. It has a Panther Point platform controller hub, PCIe WiFi and Bluetooth. It also includes a 720p webcam, USB SD reader, microphone and speakers, display port and 32GB SATA solid state drive. There is a Chrome OS EC connected on LPC, and it provides a 2560x1700 high resolution touch-enabled LCD display. > + > endchoice > > source "arch/arm/mach-at91/Kconfig" > @@ -1001,6 +1004,7 @@ source "board/woodburn/Kconfig" > source "board/work-microwave/work_92105/Kconfig" > source "board/xaeniax/Kconfig" > source "board/zipitz2/Kconfig" > +source "board/cavium/thunderx/Kconfig" > > source "arch/arm/Kconfig.debug" > > diff --git a/board/cavium/thunderx/Kconfig b/board/cavium/thunderx/Kconfig > new file mode 100644 > index 0000000..3e62abf > --- /dev/null > +++ b/board/cavium/thunderx/Kconfig > @@ -0,0 +1,19 @@ > +if TARGET_THUNDERX_88XX > + > +config SYS_CPU > + string > + default "armv8" > + > +config SYS_BOARD > + string > + default "thunderx" > + > +config SYS_VENDOR > + string > + default "cavium" > + > +config SYS_CONFIG_NAME > + string > + default "thunderx_88xx" > + > +endif > diff --git a/board/cavium/thunderx/MAINTAINERS > b/board/cavium/thunderx/MAINTAINERS > new file mode 100644 > index 0000000..c84d3b5 > --- /dev/null > +++ b/board/cavium/thunderx/MAINTAINERS > @@ -0,0 +1,6 @@ > +THUNDERX BOARD > +M: Sergey Temerkhanov <s.temerkha...@gmail.com> > +S: Maintained > +F: board/cavium/thunderx/ > +F: include/configs/thunderx_88xx.h > +F: configs/thunderx_88xx_defconfig > diff --git a/board/cavium/thunderx/Makefile b/board/cavium/thunderx/Makefile > new file mode 100644 > index 0000000..306044a > --- /dev/null > +++ b/board/cavium/thunderx/Makefile > @@ -0,0 +1,8 @@ > +# > +# > +# (C) Copyright 2014, Cavium Inc. > +# > +# SPDX-License-Identifier: GPL-2.0+ > +# > + > +obj-y := thunderx.o > diff --git a/board/cavium/thunderx/thunderx.c > b/board/cavium/thunderx/thunderx.c > new file mode 100644 > index 0000000..c478dd7 > --- /dev/null > +++ b/board/cavium/thunderx/thunderx.c > @@ -0,0 +1,86 @@ > +/** > + * (C) Copyright 2014, Cavium Inc. > + * > + * SPDX-License-Identifier: GPL-2.0+ > +**/ > + > +#include <common.h> > +#include <malloc.h> > +#include <errno.h> > +#include <linux/compiler.h> > + > +#include <dm/platdata.h> > +#include <dm/platform_data/serial_pl01x.h> > + > +static const struct pl01x_serial_platdata serial0 = { > + .base = CONFIG_SYS_SERIAL0, > + .type = TYPE_PL011, > + .clock = 0, > + .flags = PL0x_PREINITIALIZED, > +}; > + > +U_BOOT_DEVICE(thunderx_serial0) = { > + .name = "serial_pl01x", > + .platdata = &serial0, > +}; > + > +static const struct pl01x_serial_platdata serial1 = { > + .base = CONFIG_SYS_SERIAL1, > + .type = TYPE_PL011, > + .clock = 0, > + .flags = PL0x_PREINITIALIZED, > +}; > + > +U_BOOT_DEVICE(thunderx_serial1) = { > + .name = "serial_pl01x", > + .platdata = &serial1, > +}; > + As mentioned elsewhere, we should use device tree and remove this. It could be a follow-on patch if you prefer. > +DECLARE_GLOBAL_DATA_PTR; > + > +int board_init(void) > +{ > + return 0; > +} > + > +int dram_init(void) > +{ > + /* > + * Clear spin table so that secondary processors > + * observe the correct value after waken up from wfe. > + */ > + *(unsigned long *)CPU_RELEASE_ADDR = 0; > + > + gd->ram_size = PHYS_SDRAM_1_SIZE; > + return 0; > +} > + > +int timer_init(void) > +{ > + return 0; > +} > + > +/* > + * Board specific reset that is system reset. > + */ > +void reset_cpu(ulong addr) > +{ > +} > + > +/* > + * Board specific ethernet initialization routine. > + */ > +int board_eth_init(bd_t *bis) > +{ > + int rc = 0; > + > + return rc; > +} Can we use driver model for Ethernet? I.e. define CONFIG_DM_ETH. > + > +#ifdef CONFIG_PCI > +void pci_init_board(void) > +{ > + printf("DEBUG: PCI Init TODO *****\n"); > +} > +#endif When you do, please use driver model PCI. > + > diff --git a/configs/thunderx_88xx_defconfig b/configs/thunderx_88xx_defconfig > new file mode 100644 > index 0000000..9f97174 > --- /dev/null > +++ b/configs/thunderx_88xx_defconfig > @@ -0,0 +1,28 @@ > +CONFIG_SYS_EXTRA_OPTIONS="ARM64" > +CONFIG_ARM=y > +CONFIG_TARGET_THUNDERX_88XX=y > +CONFIG_SYS_PROMPT="ThunderX_88XX> " > + > +CONFIG_DM=y > +CONFIG_DM_SERIAL=y > +CONFIG_DM_STDIO=y > + > +CONFIG_CMD_CACHE=y > +CONFIG_CMD_BDI=y > +CONFIG_CMD_DIAG=y > +CONFIG_CMD_ENV=y > +CONFIG_CMD_IMI=y > +CONFIG_CMD_MEMORY=y > +CONFIG_CMD_RUN=y > +CONFIG_CMD_BOOTD=y > +CONFIG_CMD_ECHO=y > +CONFIG_CMD_SOURCE=y > + > +CONFIG_CMD_LOADB=y > +CONFIG_CMD_LOADS=y > +CONFIG_CMD_SAVES=y > + > +# CONFIG_CMD_FLASH is not set > +# CONFIG_CMD_IMLS is not set > + > +CONFIG_CMD_ATF=y > diff --git a/include/configs/thunderx_88xx.h b/include/configs/thunderx_88xx.h > new file mode 100644 > index 0000000..1973ca5 > --- /dev/null > +++ b/include/configs/thunderx_88xx.h > @@ -0,0 +1,149 @@ > +/** > + * (C) Copyright 2014, Cavium Inc. > + * > + * SPDX-License-Identifier: GPL-2.0+ > +**/ > + > +#ifndef __THUNDERX_88XX_H__ > +#define __THUNDERX_88XX_H__ > + > +#define CONFIG_REMAKE_ELF > + > +/*#define CONFIG_GICV3*/ > + > +/*#define CONFIG_ARMV8_SWITCH_TO_EL1*/ What are those two above? Perhaps add a comment as to why you have commented-out config here. > + > +#define CONFIG_SYS_GENERIC_BOARD This can go in your defconfig file. > + > +#define CONFIG_SYS_64BIT > + > +#define CONFIG_SYS_NO_FLASH > + > +/*#define CONFIG_SUPPORT_RAW_INITRD */ > + > + > +#define CONFIG_IDENT_STRING \ > + " for Cavium Thunder CN88XX ARM v8 Multi-Core" > +#define CONFIG_BOOTP_VCI_STRING "Diagnostics" > + > +#define MEM_BASE 0x00500000 > + > +#define CONFIG_COREID_MASK 0xffffff > + > +#define CONFIG_SYS_FULL_VA > + > +#define CONFIG_SYS_MEM_MAP {{0x000000000000UL, 0x40000000000UL, \ > + MT_NORMAL}, \ > + {0x800000000000UL, 0x40000000000UL, \ > + MT_DEVICE_NGNRNE}, \ > + {0x840000000000UL, 0x40000000000UL, \ > + MT_DEVICE_NGNRNE}, \ > + {0xffffffffffffUL, 0xfffffffffffUL, \ > + MT_DEVICE_NGNRNE},} > + > +#define CONFIG_SYS_MEM_MAP_SIZE 3 > + > +#define CONFIG_SYS_VA_BITS 48 > +#define CONFIG_SYS_PTL2_BITS 42 > +#define CONFIG_SYS_BLOCK_SHIFT 29 > +#define CONFIG_SYS_PTL1_ENTRIES 64 > +#define CONFIG_SYS_PTL2_ENTRIES 8192 > + > +#define CONFIG_SYS_PGTABLE_SIZE \ > + ((CONFIG_SYS_PTL1_ENTRIES + \ > + CONFIG_SYS_MEM_MAP_SIZE * CONFIG_SYS_PTL2_ENTRIES) * 8) > +#define CONFIG_SYS_TCR_EL1_IPS_BITS (5UL << 32) > +#define CONFIG_SYS_TCR_EL2_IPS_BITS (5 << 16) > +#define CONFIG_SYS_TCR_EL3_IPS_BITS (5 << 16) > + > +/* Link Definitions */ > +#define CONFIG_SYS_TEXT_BASE 0x00500000 > +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + > 0x7fff0) > + > +/* Flat Device Tree Definitions */ > +#define CONFIG_OF_LIBFDT > + > +/* SMP Spin Table Definitions */ > +#define CPU_RELEASE_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0) > + > + > +/* Generic Timer Definitions */ > +#define COUNTER_FREQUENCY (0x1800000) /* 24MHz */ > + > + > +#define CONFIG_SYS_MEMTEST_START MEM_BASE > +#define CONFIG_SYS_MEMTEST_END (MEM_BASE + PHYS_SDRAM_1_SIZE) > + > +/* Size of malloc() pool */ > +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024) > + > +/* PL011 Serial Configuration */ > + > +#define CONFIG_PL01X_SERIAL > +#define CONFIG_PL011_CLOCK 24000000 > +#define CONFIG_CONS_INDEX 1 > + > +/* Generic Interrupt Controller Definitions */ > +#define GICD_BASE (0x801000000000) > +#define GICR_BASE (0x801000002000) > +#define CONFIG_SYS_SERIAL0 0x87e024000000 > +#define CONFIG_SYS_SERIAL1 0x87e025000000 > + > +#define CONFIG_BAUDRATE 115200 > + > +/* Command line configuration */ > +#define CONFIG_MENU > + > +/* BOOTP options */ > +#define CONFIG_BOOTP_BOOTFILESIZE > +#define CONFIG_BOOTP_BOOTPATH > +#define CONFIG_BOOTP_GATEWAY > +#define CONFIG_BOOTP_HOSTNAME > +#define CONFIG_BOOTP_PXE > +#define CONFIG_BOOTP_PXE_CLIENTARCH 0x100 > + > +/* Miscellaneous configurable options */ > +#define CONFIG_SYS_LOAD_ADDR (MEM_BASE) > + > +/* Physical Memory Map */ > +#define CONFIG_NR_DRAM_BANKS 1 > +#define PHYS_SDRAM_1 (MEM_BASE) /* SDRAM Bank #1 */ > +#define PHYS_SDRAM_1_SIZE (0x80000000-MEM_BASE) /* 2048 MB */ > +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 > + > + > +/* Initial environment variables */ > +#define UBOOT_IMG_HEAD_SIZE 0x40 > +/* C80000 - 0x40 */ > +#define CONFIG_EXTRA_ENV_SETTINGS \ > + "kernel_addr=08007ffc0\0" \ > + "fdt_addr=0x94C00000\0" \ > + "fdt_high=0x9fffffff\0" > + > +#define CONFIG_BOOTARGS \ > + "console=ttyAMA0,115200n8 " \ > + "earlycon=pl011,0x87e024000000 " \ > + "debug maxcpus=48 rootwait rw "\ > + "root=/dev/sda2 coherent_pool=16M" > +#define CONFIG_BOOTDELAY 5 > + > +/* Do not preserve environment */ > +#define CONFIG_ENV_IS_NOWHERE 1 > +#define CONFIG_ENV_SIZE 0x1000 > + > +/* Monitor Command Prompt */ > +#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ > +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ > + sizeof(CONFIG_SYS_PROMPT) + 16) > +#define CONFIG_SYS_HUSH_PARSER > +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " > +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE > +#define CONFIG_SYS_LONGHELP > +#define CONFIG_CMDLINE_EDITING 1 > +#define CONFIG_SYS_MAXARGS 64 /* max command args */ > +#define CONFIG_NO_RELOCATION 1 > +#define CONFIG_LIB_RAND > +#define PLL_REF_CLK 50000000 /* 50 MHz */ > +#define NS_PER_REF_CLK_TICK (1000000000/PLL_REF_CLK) > + > +#endif /* __THUNDERX_88XX_H__ */ > -- > 2.2.0 Regards, Simon _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot