ARM supported speeds and init value of core_pll for SDP1200
are programmed wrong as part for the device speed cleanups.
Fixing it here.
Thanks to "Vitaly Andrianov <vita...@ti.com>" for bisecting this issue
Fixes: c37ed9f11b61 ("ARM: keystone2: Fix dev and arm speed detection")
Tested-by: Vitaly Andrianov <vita...@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvu...@ti.com>
---
arch/arm/mach-keystone/include/mach/clock-k2l.h | 4 ++--
board/ti/ks2_evm/board_k2l.c | 2 +-
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-keystone/include/mach/clock-k2l.h
b/arch/arm/mach-keystone/include/mach/clock-k2l.h
index 8772a7d..dec1939 100644
--- a/arch/arm/mach-keystone/include/mach/clock-k2l.h
+++ b/arch/arm/mach-keystone/include/mach/clock-k2l.h
@@ -40,7 +40,7 @@
/* k2l DEV supports 800, 1000, 1200 MHz */
#define DEV_SUPPORTED_SPEEDS 0x383
-/* k2l ARM supportd 800, 1000, 1200, MHz */
-#define ARM_SUPPORTED_SPEEDS 0x383
+/* k2l ARM supportd 800, 1000, 1200, 1350, 1400 MHz */
+#define ARM_SUPPORTED_SPEEDS 0x3ef
#endif
diff --git a/board/ti/ks2_evm/board_k2l.c b/board/ti/ks2_evm/board_k2l.c
index 70e25f1..f35a64f 100644
--- a/board/ti/ks2_evm/board_k2l.c
+++ b/board/ti/ks2_evm/board_k2l.c
@@ -25,7 +25,7 @@ unsigned int external_clk[ext_clk_count] = {
static struct pll_init_data core_pll_config[NUM_SPDS] = {
[SPD800] = CORE_PLL_799,
[SPD1000] = CORE_PLL_1000,
- [SPD800] = CORE_PLL_1198,
+ [SPD1200] = CORE_PLL_1198,
};
s16 divn_val[16] = {
--
2.1.4
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