On Fri, Jul 24, 2015 at 09:22:14AM +0200, Alexander Stein wrote: > This adds dcache support for dwc2. The DMA buffers must be DMA aligned and > is flushed for outgoing transactions before starting transfer. For > ingoing transactions it is invalidated after the transfer has finished. > > Signed-off-by: Alexander Stein <alexander...@web.de> > Acked-by: Stephen Warren <swar...@wwwdotorg.org>
Applied to u-boot/master, thanks! -- Tom
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