On Sat, Jul 18, 2015 at 03:07:52AM +0300, Vladimir Zapolskiy wrote: > The change adds support of LPC32xx SLC NAND controller. > > LPC32xx SoC has two different mutually exclusive NAND controllers to > communicate with single and multiple layer chips. > > This simple driver allows to specify NAND chip timings and defines > custom read_buf()/write_buf() operations, because access to 8-bit data > register must be 32-bit aligned. > > Support of hardware ECC calculation is not implemented (data > correction is always done by software), since it requires a working > DMA engine. > > The driver can be included to an SPL image. > > Signed-off-by: Vladimir Zapolskiy <v...@mleia.com> > Acked-by: Scott Wood <scottw...@freescale.com> > Tested-by: Sylvain Lemieux <slemi...@tycoint.com>
Applied to u-boot/master, thanks! -- Tom
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