Hi Wolfgang and Stefan,
Wolfgang Denk schrieb:
> Of course you can. The cure is simple:
>
> Fix "include/ppc405.h" so we get rid of this silly "base address +
> offset" notation and use proper C structures instead.
>
>
> Oh, and while we are at it - "include/ppc440.h" has more of this stuff
> that is waiting for cleanup. But that is another story, not related to
> your patch - maybe Stefan picks up this ball :-)
>
>
>> We could put the cast into the GPIO_IR (and friends) definitions.
>
> No cast is needed. Just use proper C structs.
>
>> Do you want me to remove the cast and life with a compiler warning until
>> this has been globally fixed?
>
> No, of course not.
>
>> Because this is not a particular problem with this patch it should be
>> addressed in a separate discussion. But you are rigth - this cast is
>> a little bit nerving :-)
>
> I agree - the cleanup patch should be submitted first.
Do you want to see something like this (see below)?
I ran into the problem that include/ppc405.h defines a macro "tcr".
This conflicts with tcr in my gpio_controller struct.
When this kind of structure and it's usage is ok,
I will provide a clean patch that adds the struct
and a revised path for adding the PMC405DE board support.
I hope you do make adding PMC405DE board support dependant from
fixing all casts with io accessor macros :-(
Matthias
---
board/esd/pmc405de/pmc405de.c | 30 +++++++++++++++++++++---------
include/asm-ppc/gpio.h | 24 ++++++++++++++++++++++++
2 files changed, 45 insertions(+), 9 deletions(-)
diff --git a/board/esd/pmc405de/pmc405de.c b/board/esd/pmc405de/pmc405de.c
index 9c1a119..789e326 100644
--- a/board/esd/pmc405de/pmc405de.c
+++ b/board/esd/pmc405de/pmc405de.c
@@ -26,10 +26,20 @@
#include <fdt_support.h>
#include <asm/processor.h>
#include <asm/io.h>
+#include <asm/gpio.h>
#include <asm/4xx_pci.h>
#include <command.h>
#include <malloc.h>
+struct pmc405de_cpld {
+ u8 version;
+ u8 reserved0[3];
+ u8 status;
+ u8 reserved1[3];
+ u8 control;
+ u8 reserved2[3];
+};
+
#define CPLD_VERSION (CONFIG_SYS_CPLD_BASE + 0)
#define CPLD_VERSION_MASK 0x0f
#define CPLD_STATUS (CONFIG_SYS_CPLD_BASE + 4)
@@ -120,22 +130,24 @@ static void upd_plb_pci_div(u32 pllmr0, u32
pllmr1, u32 div)
int misc_init_r(void)
{
int i;
+ struct ppc4xx_gpio_controller *gpio0 = (struct ppc4xx_gpio_controller
*)GPIO_BASE;
+ struct pmc405de_cpld *cpld = (struct pmc405de_cpld
*)CONFIG_SYS_CPLD_BASE;
if (!is_monarch()) {
/* PCI configuration done: release EREADY */
- out_be32((void*)GPIO0_OR,
- in_be32((void*)GPIO0_OR) | CONFIG_SYS_GPIO_EREADY);
- out_be32((void*)GPIO0_TCR,
- in_be32((void*)GPIO0_TCR) | CONFIG_SYS_GPIO_EREADY);
+ out_be32(&gpio0->or,
+ in_be32(&gpio0->or) | CONFIG_SYS_GPIO_EREADY);
+ out_be32(&gpio0->_tcr,
+ in_be32(&gpio0->_tcr) | CONFIG_SYS_GPIO_EREADY);
}
/* turn off POST LED */
- out_8((void*)CPLD_CONTROL,
+ out_8(&cpld->control,
CPLD_CONTROL_POSTLED_N | CPLD_CONTROL_POSTLED_GATE);
/* turn on LEDs: RUN, A, B */
- out_be32((void*)GPIO0_OR,
- in_be32((void*)GPIO0_OR) &
+ out_be32(&gpio0->or,
+ in_be32(&gpio0->or) &
~(CONFIG_SYS_GPIO_LEDRUN_N |
CONFIG_SYS_GPIO_LEDA_N |
CONFIG_SYS_GPIO_LEDB_N));
@@ -144,8 +156,8 @@ int misc_init_r(void)
udelay(1000);
/* turn off LEDs: A, B */
- out_be32((void*)GPIO0_OR,
- in_be32((void*)GPIO0_OR) |
+ out_be32(&gpio0->or,
+ in_be32(&gpio0->or) |
(CONFIG_SYS_GPIO_LEDA_N |
CONFIG_SYS_GPIO_LEDB_N));
diff --git a/include/asm-ppc/gpio.h b/include/asm-ppc/gpio.h
index fc05dc0..2dfbad7 100644
--- a/include/asm-ppc/gpio.h
+++ b/include/asm-ppc/gpio.h
@@ -24,6 +24,8 @@
#ifndef __ASM_PPC_GPIO_H
#define __ASM_PPC_GPIO_H
+#include <asm/types.h>
+
/* 4xx PPC's have 2 GPIO controllers */
#if defined(CONFIG_405EZ) || \
defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
@@ -34,6 +36,28 @@
#define GPIO_GROUP_MAX 1
#endif
+/* GPIO controller */
+struct ppc4xx_gpio_controller {
+ u32 or;
+ u32 _tcr;
+ u32 osl;
+ u32 osh;
+ u32 tsl;
+ u32 tsh;
+ u32 odr;
+ u32 ir;
+ u32 rr1;
+ u32 rr2;
+ u32 rr3;
+ u32 reserved;
+ u32 is1l;
+ u32 is1h;
+ u32 is2l;
+ u32 is2h;
+ u32 is3l;
+ u32 is3h;
+};
+
/* Offsets */
#define GPIOx_OR 0x00 /* GPIO Output Register */
#define GPIOx_TCR 0x04 /* GPIO Three-State Control Register */
--
1.6.1
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