On Wednesday, June 03, 2015 at 05:52:47 AM, dingu...@opensource.altera.com
wrote:
> From: Dinh Nguyen <dingu...@opensource.altera.com>
>
> Hi,
>
> This is v4 of the patch series that adds the DDR controller driver for
> Altera's SoCFPGA platform.
>
> v4:
> - Further cleanup by removing comments that do not apply for Cyclone5.
> - Removed more unused functions
>
> Thanks,
I applied this to u-boot/master and tried building for socfpga_cyclone5,
this is what I'm getting after I fixed these patches to actually apply
to u-boot/master (there was a minor conflict in Makefile):
drivers/ddr/altera/sdram.c:11:35: fatal error: asm/arch/sdram_config.h: No such
file or directory
#include <asm/arch/sdram_config.h>
^
compilation terminated.
make[1]: *** [drivers/ddr/altera/sdram.o] Error 1
make[1]: *** Waiting for unfinished jobs....
drivers/ddr/altera/sequencer.c: In function 'sdr_get_addr':
drivers/ddr/altera/sequencer.c:108:32: error: 'SDR_CTRLGRP_ADDRESS' undeclared
(first use in this function)
addr = ((u32)base & 0xfff) | SDR_CTRLGRP_ADDRESS;
^
drivers/ddr/altera/sequencer.c:108:32: note: each undeclared identifier is
reported only once for each function it appears in
drivers/ddr/altera/sequencer.c: In function 'initialize_hps_phy':
drivers/ddr/altera/sequencer.c:3850:2: warning: implicit declaration of
function
'SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ACDELAYEN_SET' [-Wimplicit-function-declaration]
reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ACDELAYEN_SET(2);
Am I missing something ?
Best regards,
Marek Vasut
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