Hi Stefano,
On Wed, Jun 10, 2015 at 11:23:10AM +0200, Stefano Babic wrote:
>Hi Peng,
>
>On 10/06/2015 10:06, Peng Fan wrote:
>> Since i.MX6QP changes some CCM registers, so modify the clocks settings to
>> follow the hardware changes.
>>
>> A new CONFIG_MX6QP is introduced here and is used for the CCM difference.
>> At default CONFIG_MX6Q is enabled along with the CONFIG_MX6QP.
>>
>> Signed-off-by: Ye.Li <b37...@freescale.com>
>> Signed-off-by: Peng Fan <peng....@freescale.com>
>> ---
>> arch/arm/cpu/armv7/mx6/clock.c | 13 +++++---
>> arch/arm/cpu/armv7/mx6/soc.c | 5 ++-
>> arch/arm/include/asm/arch-mx6/crm_regs.h | 55
>> ++++++++++++++++++++++++--------
>> include/configs/mx6_common.h | 3 ++
>> 4 files changed, 57 insertions(+), 19 deletions(-)
>>
>> diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c
>> index ae99945..36cd5a8 100644
>> --- a/arch/arm/cpu/armv7/mx6/clock.c
>> +++ b/arch/arm/cpu/armv7/mx6/clock.c
>> @@ -323,7 +323,7 @@ static u32 get_ipg_per_clk(void)
>> u32 reg, perclk_podf;
>>
>> reg = __raw_readl(&imx_ccm->cscmr1);
>> -#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX))
>> +#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX) ||
>> defined(CONFIG_MX6QP))
>> if (reg & MXC_CCM_CSCMR1_PER_CLK_SEL_MASK)
>> return MXC_HCLK; /* OSC 24Mhz */
>
>I have a general issue. We already manage to have support for multiple
>variants of MX6 (at least, dual/quad/solo) with a single image. We get
>it dropping nasty #ifdef in case of quad/dual. I assume there are only
>slight changes in layout for the 6QP. Cannot we manage these changes at
>runtime instead of introducing a compiler switch ?
Yeah, better do runtime check. Will fix this in v2.
>
>> #endif
>> @@ -337,7 +337,7 @@ static u32 get_uart_clk(void)
>> u32 reg, uart_podf;
>> u32 freq = decode_pll(PLL_USBOTG, MXC_HCLK) / 6; /* static divider */
>> reg = __raw_readl(&imx_ccm->cscdr1);
>> -#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX))
>> +#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX) ||
>> defined(CONFIG_MX6QP))
>> if (reg & MXC_CCM_CSCDR1_UART_CLK_SEL)
>> freq = MXC_HCLK;
>> #endif
>> @@ -352,8 +352,13 @@ static u32 get_cspi_clk(void)
>> u32 reg, cspi_podf;
>>
>> reg = __raw_readl(&imx_ccm->cscdr2);
>> - reg &= MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK;
>> - cspi_podf = reg >> MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET;
>> + cspi_podf = (reg & MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK)
>> + >> MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET;
>> +
>> +#if defined(CONFIG_MX6QP)
>> + if (reg & MXC_CCM_CSCDR2_ECSPI_CLK_SEL_MASK)
>> + return MXC_HCLK / (cspi_podf + 1);
>> +#endif
>>
>> return decode_pll(PLL_USBOTG, MXC_HCLK) / (8 * (cspi_podf + 1));
>> }
>> diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
>> index e3474e7..5eea9d9 100644
>> --- a/arch/arm/cpu/armv7/mx6/soc.c
>> +++ b/arch/arm/cpu/armv7/mx6/soc.c
>> @@ -335,9 +335,12 @@ static void set_ahb_rate(u32 val)
>> static void clear_mmdc_ch_mask(void)
>> {
>> struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
>> + u32 reg;
>> + reg = readl(&mxc_ccm->ccdr);
>>
>> /* Clear MMDC channel mask */
>> - writel(0, &mxc_ccm->ccdr);
>> + reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK | MXC_CCM_CCDR_MMDC_CH0_HS_MASK);
>> + writel(reg, &mxc_ccm->ccdr);
>> }
>>
>> static void init_bandgap(void)
>> diff --git a/arch/arm/include/asm/arch-mx6/crm_regs.h
>> b/arch/arm/include/asm/arch-mx6/crm_regs.h
>> index 887d048..576dabe 100644
>> --- a/arch/arm/include/asm/arch-mx6/crm_regs.h
>> +++ b/arch/arm/include/asm/arch-mx6/crm_regs.h
>> @@ -113,7 +113,7 @@ struct mxc_ccm_reg {
>> #define MXC_CCM_CCR_WB_COUNT_MASK 0x7
>> #define MXC_CCM_CCR_WB_COUNT_OFFSET (1 << 16)
>> #define MXC_CCM_CCR_COSC_EN (1 << 12)
>> -#ifdef CONFIG_MX6SX
>> +#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6QP))
>> #define MXC_CCM_CCR_OSCNT_MASK 0x7F
>> #else
>> #define MXC_CCM_CCR_OSCNT_MASK 0xFF
>> @@ -123,6 +123,9 @@ struct mxc_ccm_reg {
>> /* Define the bits in register CCDR */
>> #define MXC_CCM_CCDR_MMDC_CH1_HS_MASK (1 << 16)
>> #define MXC_CCM_CCDR_MMDC_CH0_HS_MASK (1 << 17)
>> +#ifdef CONFIG_MX6QP
>> +#define MXC_CCM_CCDR_MMDC_CH1_AXI_ROOT_CG (1 << 18)
>> +#endif
>>
>> /* Define the bits in register CSR */
>> #define MXC_CCM_CSR_COSC_READY (1 << 5)
>> @@ -196,7 +199,11 @@ struct mxc_ccm_reg {
>> #define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_MASK (0x3 << 4)
>> #define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_OFFSET 4
>> #ifndef CONFIG_MX6SX
>> +#ifdef CONFIG_MX6QP
>> +#define MXC_CCM_CBCMR_PRE_CLK_SEL (1 << 1)
>> +#else
>> #define MXC_CCM_CBCMR_GPU3D_AXI_CLK_SEL (1 << 1)
>> +#endif
>> #define MXC_CCM_CBCMR_GPU2D_AXI_CLK_SEL (1 << 0)
>> #endif
>>
>> @@ -229,7 +236,7 @@ struct mxc_ccm_reg {
>> #define MXC_CCM_CSCMR1_QSPI1_CLK_SEL_MASK (0x7 << 7)
>> #define MXC_CCM_CSCMR1_QSPI1_CLK_SEL_OFFSET 7
>> #endif
>> -#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX))
>> +#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX) ||
>> defined(CONFIG_MX6QP))
>> #define MXC_CCM_CSCMR1_PER_CLK_SEL_MASK (1 << 6)
>> #define MXC_CCM_CSCMR1_PER_CLK_SEL_OFFSET 6
>> #endif
>> @@ -244,15 +251,12 @@ struct mxc_ccm_reg {
>> #define MXC_CCM_CSCMR2_ESAI_PRE_SEL_OFFSET 19
>> #define MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV (1 << 11)
>> #define MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV (1 << 10)
>> -#ifdef CONFIG_MX6SX
>> +#if (defined(CONFIG_MX6SX) || defined(CONFIG_MX6QP))
>> #define MXC_CCM_CSCMR2_CAN_CLK_SEL_MASK (0x3 << 8)
>> #define MXC_CCM_CSCMR2_CAN_CLK_SEL_OFFSET 8
>> +#endif
>> #define MXC_CCM_CSCMR2_CAN_CLK_PODF_MASK (0x3F << 2)
>> #define MXC_CCM_CSCMR2_CAN_CLK_PODF_OFFSET 2
>> -#else
>> -#define MXC_CCM_CSCMR2_CAN_CLK_SEL_MASK (0x3F << 2)
>> -#define MXC_CCM_CSCMR2_CAN_CLK_SEL_OFFSET 2
>> -#endif
>>
>> /* Define the bits in register CSCDR1 */
>> #ifndef CONFIG_MX6SX
>> @@ -273,15 +277,10 @@ struct mxc_ccm_reg {
>> #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET 6
>> #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK (0x3 << 6)
>> #endif
>> -#ifdef CONFIG_MX6SL
>> -#define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK 0x1F
>> -#define MXC_CCM_CSCDR1_UART_CLK_SEL (1 << 6)
>> -#else
>> -#define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK 0x3F
>> -#ifdef CONFIG_MX6SX
>> +#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX) ||
>> defined(CONFIG_MX6QP))
>> #define MXC_CCM_CSCDR1_UART_CLK_SEL (1 << 6)
>> #endif
>> -#endif
>> +#define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK 0x3F
>> #define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET 0
>>
>> /* Define the bits in register CS1CDR */
>> @@ -316,10 +315,17 @@ struct mxc_ccm_reg {
>> #define MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK (0x7 << 18)
>> #define MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET 18
>> #define MXC_CCM_CS2CDR_ENFC_CLK_PRED(v) (((v) & 0x7) <<
>> 18)
>> +
>> +#ifdef CONFIG_MX6QP
>> +#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK (0x7 << 15)
>> +#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET 15
>> +#define MXC_CCM_CS2CDR_ENFC_CLK_SEL(v) (((v) & 0x7) <<
>> 15)
>> +#else
>> #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK (0x3 << 16)
>> #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET 16
>> #define MXC_CCM_CS2CDR_ENFC_CLK_SEL(v) (((v) & 0x3) <<
>> 16)
>> #endif
>> +#endif
>> #define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK (0x7 << 12)
>> #define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET 12
>> #define MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK (0x7 << 9)
>> @@ -384,6 +390,11 @@ struct mxc_ccm_reg {
>> /* Define the bits in register CSCDR2 */
>> #define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK (0x3F << 19)
>> #define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET 19
>> +#ifdef CONFIG_MX6QP
>> +#define MXC_CCM_CSCDR2_ECSPI_CLK_SEL_MASK (0x1 << 18)
>> +#define MXC_CCM_CSCDR2_ECSPI_CLK_SEL_OFFSET 18
>> +#endif
>> +
>> /* All IPU2_DI1 are LCDIF1 on MX6SX */
>> #define MXC_CCM_CHSCCDR_IPU2_DI1_PRE_CLK_SEL_MASK (0x7 << 15)
>> #define MXC_CCM_CHSCCDR_IPU2_DI1_PRE_CLK_SEL_OFFSET 15
>> @@ -758,6 +769,22 @@ struct mxc_ccm_reg {
>> #else
>> #define MXC_CCM_CCGR6_VDOAXICLK_OFFSET 12
>> #define MXC_CCM_CCGR6_VDOAXICLK_MASK (3 <<
>> MXC_CCM_CCGR6_VDOAXICLK_OFFSET)
>> +#ifdef CONFIG_MX6QP
>> +#define MXC_CCM_CCGR6_VPUCLK_OFFSET 14
>> +#define MXC_CCM_CCGR6_VPUCLK_MASK (3 << MXC_CCM_CCGR6_VPUCLK_OFFSET)
>> +#define MXC_CCM_CCGR6_PRE_CLK0_OFFSET 16
>> +#define MXC_CCM_CCGR6_PRE_CLK0_MASK (3 << MXC_CCM_CCGR6_PRE_CLK0_OFFSET)
>> +#define MXC_CCM_CCGR6_PRE_CLK1_OFFSET 18
>> +#define MXC_CCM_CCGR6_PRE_CLK1_MASK (3 << MXC_CCM_CCGR6_PRE_CLK1_OFFSET)
>> +#define MXC_CCM_CCGR6_PRE_CLK2_OFFSET 20
>> +#define MXC_CCM_CCGR6_PRE_CLK2_MASK (3 << MXC_CCM_CCGR6_PRE_CLK2_OFFSET)
>> +#define MXC_CCM_CCGR6_PRE_CLK3_OFFSET 22
>> +#define MXC_CCM_CCGR6_PRE_CLK3_MASK (3 << MXC_CCM_CCGR6_PRE_CLK3_OFFSET)
>> +#define MXC_CCM_CCGR6_PRG_CLK0_OFFSET 24
>> +#define MXC_CCM_CCGR6_PRG_CLK0_MASK (3 << MXC_CCM_CCGR6_PRG_CLK0_OFFSET)
>> +#define MXC_CCM_CCGR6_PRG_CLK1_OFFSET 26
>> +#define MXC_CCM_CCGR6_PRG_CLK1_MASK (3 << MXC_CCM_CCGR6_PRG_CLK1_OFFSET)
>> +#endif
>> #endif
>>
>> #define BM_ANADIG_PLL_SYS_LOCK 0x80000000
>> diff --git a/include/configs/mx6_common.h b/include/configs/mx6_common.h
>> index 50370e1..b5de280 100644
>> --- a/include/configs/mx6_common.h
>> +++ b/include/configs/mx6_common.h
>> @@ -30,6 +30,9 @@
>>
>> #define CONFIG_MP
>> #define CONFIG_MXC_GPT_HCLK
>> +#ifdef CONFIG_MX6QP
>> +#define CONFIG_MX6Q
>> +#endif
>>
>> #define CONFIG_SYS_NO_FLASH
>>
>>
>
>Best regards,
>Stefano Babic
>
>--
>=====================================================================
>DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
>HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
>Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de
>=====================================================================
Regards,
Peng
--
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