This adds PSCI support for sun6i. So far it only supports
the PWR_ON method.
Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
arch/arm/cpu/armv7/sunxi/Makefile | 1 +
arch/arm/cpu/armv7/sunxi/psci_sun6i.S | 276 ++++++++++++++++++++++++++++++++++
2 files changed, 277 insertions(+)
create mode 100644 arch/arm/cpu/armv7/sunxi/psci_sun6i.S
diff --git a/arch/arm/cpu/armv7/sunxi/Makefile
b/arch/arm/cpu/armv7/sunxi/Makefile
index 85fbc85..4b783e0 100644
--- a/arch/arm/cpu/armv7/sunxi/Makefile
+++ b/arch/arm/cpu/armv7/sunxi/Makefile
@@ -35,6 +35,7 @@ obj-$(CONFIG_AXP221_POWER) += pmic_bus.o
ifndef CONFIG_SPL_BUILD
ifdef CONFIG_ARMV7_PSCI
+obj-$(CONFIG_MACH_SUN6I) += psci_sun6i.o
obj-$(CONFIG_MACH_SUN7I) += psci_sun7i.o
endif
endif
diff --git a/arch/arm/cpu/armv7/sunxi/psci_sun6i.S
b/arch/arm/cpu/armv7/sunxi/psci_sun6i.S
new file mode 100644
index 0000000..2516804
--- /dev/null
+++ b/arch/arm/cpu/armv7/sunxi/psci_sun6i.S
@@ -0,0 +1,276 @@
+/*
+ * Copyright (C) 2015 - Chen-Yu Tsai
+ * Author: Chen-Yu Tsai <w...@csie.org>
+ *
+ * Based on psci_sun7i.S by Marc Zyngier <marc.zyng...@arm.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <config.h>
+#include <asm/gic.h>
+#include <asm/macro.h>
+#include <asm/psci.h>
+#include <asm/arch/cpu.h>
+
+/*
+ * Memory layout:
+ *
+ * SECURE_RAM to text_end :
+ * ._secure_text section
+ * text_end to ALIGN_PAGE(text_end):
+ * nothing
+ * ALIGN_PAGE(text_end) to ALIGN_PAGE(text_end) + 0x1000)
+ * 1kB of stack per CPU (4 CPUs max).
+ */
+
+ .pushsection ._secure.text, "ax"
+
+ .arch_extension sec
+
+#define ONE_MS (CONFIG_TIMER_CLK_FREQ / 1000)
+#define TEN_MS (10 * ONE_MS)
+#define GICD_BASE 0x1c81000
+#define GICC_BASE 0x1c82000
+
+.macro timer_wait reg, ticks
+ @ Program CNTP_TVAL
+ movw \reg, #(\ticks & 0xffff)
+ movt \reg, #(\ticks >> 16)
+ mcr p15, 0, \reg, c14, c2, 0
+ isb
+ @ Enable physical timer, mask interrupt
+ mov \reg, #3
+ mcr p15, 0, \reg, c14, c2, 1
+ @ Poll physical timer until ISTATUS is on
+1: isb
+ mrc p15, 0, \reg, c14, c2, 1
+ ands \reg, \reg, #4
+ bne 1b
+ @ Disable timer
+ mov \reg, #0
+ mcr p15, 0, \reg, c14, c2, 1
+ isb
+.endm
+
