Hi Heiko, On 12/04/2015 10:24, Heiko Schocher wrote: > add support for imx6dl based aristainetos2 board > > U-Boot 2015.04-rc5-00066-g60f6ed4 (Apr 10 2015 - 08:46:27) > > CPU: Freescale i.MX6DL rev1.1 at 792 MHz > Reset cause: WDOG > Board: aristaitenos2 > Watchdog enabled > I2C: ready > DRAM: 1 GiB > NAND: 1024 MiB > MMC: FSL_SDHC: 0 > SF: Detected N25Q128A with page size 256 Bytes, erase size 64 KiB, total 16 > MiB > Display: lg4573 (480x800) > In: serial > Out: serial > Err: serial > Net: FEC [PRIME] > Hit any key to stop autoboot: 0 > => > > Signed-off-by: Heiko Schocher <h...@denx.de> > --- > > arch/arm/Kconfig | 5 + > board/aristainetos2/Kconfig | 12 + > board/aristainetos2/MAINTAINERS | 6 + > board/aristainetos2/Makefile | 12 + > board/aristainetos2/aristainetos2.c | 917 > ++++++++++++++++++++++++++++++++++ > board/aristainetos2/aristainetos2.cfg | 34 ++ > board/aristainetos2/axi.cfg | 22 + > board/aristainetos2/clocks.cfg | 24 + > board/aristainetos2/ddr-setup.cfg | 59 +++ > board/aristainetos2/nt5cc256m16cp.cfg | 60 +++ > configs/aristainetos2_defconfig | 3 + > include/configs/aristainetos2.h | 351 +++++++++++++ > 12 files changed, 1505 insertions(+) > create mode 100644 board/aristainetos2/Kconfig > create mode 100644 board/aristainetos2/MAINTAINERS > create mode 100644 board/aristainetos2/Makefile > create mode 100644 board/aristainetos2/aristainetos2.c > create mode 100644 board/aristainetos2/aristainetos2.cfg > create mode 100644 board/aristainetos2/axi.cfg > create mode 100644 board/aristainetos2/clocks.cfg > create mode 100644 board/aristainetos2/ddr-setup.cfg > create mode 100644 board/aristainetos2/nt5cc256m16cp.cfg > create mode 100644 configs/aristainetos2_defconfig > create mode 100644 include/configs/aristainetos2.h > > diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig > index 80b0d34..ea4923f 100644 > --- a/arch/arm/Kconfig > +++ b/arch/arm/Kconfig > @@ -501,6 +501,10 @@ config TARGET_ARISTAINETOS > bool "Support aristainetos" > select CPU_V7 > > +config TARGET_ARISTAINETOS2 > + bool "Support aristainetos2" > + select CPU_V7 > + > config TARGET_MX6QARM2 > bool "Support mx6qarm2" > select CPU_V7 > @@ -765,6 +769,7 @@ source "arch/arm/cpu/armv8/Kconfig" > source "arch/arm/imx-common/Kconfig" > > source "board/aristainetos/Kconfig" > +source "board/aristainetos2/Kconfig" > source "board/BuR/kwb/Kconfig" > source "board/BuR/tseries/Kconfig" > source "board/CarMediaLab/flea3/Kconfig" > diff --git a/board/aristainetos2/Kconfig b/board/aristainetos2/Kconfig > new file mode 100644 > index 0000000..2cf13e4 > --- /dev/null > +++ b/board/aristainetos2/Kconfig > @@ -0,0 +1,12 @@ > +if TARGET_ARISTAINETOS2 > + > +config SYS_BOARD > + default "aristainetos2" > + > +config SYS_SOC > + default "mx6" > + > +config SYS_CONFIG_NAME > + default "aristainetos2" > + > +endif > diff --git a/board/aristainetos2/MAINTAINERS b/board/aristainetos2/MAINTAINERS > new file mode 100644 > index 0000000..d155f86 > --- /dev/null > +++ b/board/aristainetos2/MAINTAINERS > @@ -0,0 +1,6 @@ > +ARISTAINETOS BOARD > +M: Heiko Schocher <h...@denx.de> > +S: Maintained > +F: board/aristainetos2/ > +F: include/configs/aristainetos2.h > +F: configs/aristainetos2_defconfig > diff --git a/board/aristainetos2/Makefile b/board/aristainetos2/Makefile > new file mode 100644 > index 0000000..2513744 > --- /dev/null > +++ b/board/aristainetos2/Makefile > @@ -0,0 +1,12 @@ > +# > +# (C) Copyright 2015 > +# Heiko Schocher, DENX Software Engineering, h...@denx.de. > +# > +# Copyright (C) 2007, Guennadi Liakhovetski <l...@denx.de> > +# > +# (C) Copyright 2011 Freescale Semiconductor, Inc. > +# > +# SPDX-License-Identifier: GPL-2.0+ > +# > + > +obj-y := aristainetos2.o > diff --git a/board/aristainetos2/aristainetos2.c > b/board/aristainetos2/aristainetos2.c > new file mode 100644 > index 0000000..98e1bc7 > --- /dev/null > +++ b/board/aristainetos2/aristainetos2.c > @@ -0,0 +1,917 @@ > +/* > + * (C) Copyright 2015 > + * Heiko Schocher, DENX Software Engineering, h...@denx.de. > + * > + * Based on: > + * Copyright (C) 2012 Freescale Semiconductor, Inc. > + * > + * Author: Fabio Estevam <fabio.este...@freescale.com> > + * > + * SPDX-License-Identifier: GPL-2.0+ > + */ > + > +#include <asm/arch/clock.h> > +#include <asm/arch/imx-regs.h> > +#include <asm/arch/iomux.h> > +#include <asm/arch/mx6-pins.h> > +#include <asm/errno.h> > +#include <asm/gpio.h> > +#include <asm/imx-common/iomux-v3.h> > +#include <asm/imx-common/boot_mode.h> > +#include <asm/imx-common/mxc_i2c.h> > +#include <asm/imx-common/video.h> > +#include <mmc.h> > +#include <fsl_esdhc.h> > +#include <micrel.h> > +#include <miiphy.h> > +#include <netdev.h> > +#include <asm/arch/mxc_hdmi.h> > +#include <asm/arch/crm_regs.h> > +#include <linux/fb.h> > +#include <ipu_pixfmt.h> > +#include <asm/io.h> > +#include <asm/arch/sys_proto.h> > +#include <pwm.h> > +#include <spi.h> > +#include <video.h> > +#include <../drivers/video/ipu.h> > +#if defined(CONFIG_VIDEO_BMP_LOGO) > + #include <bmp_logo.h> > +#endif > +DECLARE_GLOBAL_DATA_PTR; > + > +#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ > + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ > + PAD_CTL_SRE_FAST | PAD_CTL_HYS) > + > +#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ > + PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ > + PAD_CTL_SRE_FAST | PAD_CTL_HYS) > + > +#define USDHC2_PAD_CTRL (PAD_CTL_SPEED_LOW | \ > + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) > + > +#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ > + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) > + > +#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \ > + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) > + > +#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ > + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ > + PAD_CTL_ODE | PAD_CTL_SRE_FAST) > + > +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) > + > +#define DISP_PAD_CTRL (0x10) > + > +#define ECSPI1_CS0 IMX_GPIO_NR(4, 9) /* 4.3 display controller */ > +#define ECSPI4_CS0 IMX_GPIO_NR(3, 29) > +#define ECSPI4_CS1 IMX_GPIO_NR(5, 2) /* NOR boot flash */ > + > +#define SOFT_RESET_GPIO IMX_GPIO_NR(7, 13) > +#define SD2_DRIVER_ENABLE IMX_GPIO_NR(7, 8) > + > + > +struct i2c_pads_info i2c_pad_info1 = { > + .scl = { > + .i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | PC, > + .gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27 | PC, > + .gp = IMX_GPIO_NR(5, 27) > + }, > + .sda = { > + .i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA | PC, > + .gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26 | PC, > + .gp = IMX_GPIO_NR(5, 26) > + } > +}; > + > +struct i2c_pads_info i2c_pad_info2 = { > + .scl = { > + .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | PC, > + .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | PC, > + .gp = IMX_GPIO_NR(4, 12) > + }, > + .sda = { > + .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC, > + .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | PC, > + .gp = IMX_GPIO_NR(4, 13) > + } > +}; > + > +struct i2c_pads_info i2c_pad_info3 = { > + .scl = { > + .i2c_mode = MX6_PAD_GPIO_5__I2C3_SCL | PC, > + .gpio_mode = MX6_PAD_GPIO_5__GPIO1_IO05 | PC, > + .gp = IMX_GPIO_NR(1, 5) > + }, > + .sda = { > + .i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA | PC, > + .gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06 | PC, > + .gp = IMX_GPIO_NR(1, 6) > + } > +}; > + > +struct i2c_pads_info i2c_pad_info4 = { > + .scl = { > + .i2c_mode = MX6_PAD_GPIO_7__I2C4_SCL | PC, > + .gpio_mode = MX6_PAD_GPIO_7__GPIO1_IO07 | PC, > + .gp = IMX_GPIO_NR(1, 7) > + }, > + .sda = { > + .i2c_mode = MX6_PAD_GPIO_8__I2C4_SDA | PC, > + .gpio_mode = MX6_PAD_GPIO_8__GPIO1_IO08 | PC, > + .gp = IMX_GPIO_NR(1, 8) > + } > +}; > + > +static int lgdisplay;
It looks like strange to pass a parameter via a global variable. No other way ? > + > +int dram_init(void) > +{ > + gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); > + > + return 0; > +} > + > +iomux_v3_cfg_t const uart1_pads[] = { > + MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), > + MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), > + MX6_PAD_EIM_D19__UART1_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), > + MX6_PAD_EIM_D20__UART1_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), > +}; > + > +iomux_v3_cfg_t const uart2_pads[] = { > + MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), > + MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), > +}; > + > +iomux_v3_cfg_t const uart3_pads[] = { > + MX6_PAD_EIM_D24__UART3_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), > + MX6_PAD_EIM_D25__UART3_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), > + MX6_PAD_EIM_D31__UART3_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), > + MX6_PAD_EIM_D23__UART3_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), > +}; > + > +iomux_v3_cfg_t const uart4_pads[] = { > + MX6_PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), > + MX6_PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), > +}; > + > +iomux_v3_cfg_t const gpio_pads[] = { > + /* LED enable*/ > + MX6_PAD_ENET_CRS_DV__GPIO1_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL), > + /* LED yellow */ > + MX6_PAD_NANDF_CS3__GPIO6_IO16 | MUX_PAD_CTRL(NO_PAD_CTRL), > + /* LED red */ > + MX6_PAD_EIM_EB0__GPIO2_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL), > + /* LED green */ > + MX6_PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL), > + /* LED blue */ > + MX6_PAD_EIM_EB1__GPIO2_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL), > + /* spi flash WP protect */ > + MX6_PAD_SD4_DAT7__GPIO2_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL), > + /* spi CS 0 */ > + MX6_PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL), > + /* spi bus #2 SS driver enable */ > + MX6_PAD_EIM_A23__GPIO6_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL), > + /* RST_LOC# PHY reset input (has pull-down!)*/ > + MX6_PAD_GPIO_18__GPIO7_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL), > + /* SD 2 level shifter output enable */ > + MX6_PAD_SD3_RST__GPIO7_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL), > + /* SD1 card detect input */ > + MX6_PAD_ENET_RXD0__GPIO1_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL), > + /* SD1 write protect input */ > + MX6_PAD_DI0_PIN4__GPIO4_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL), > + /* SD2 card detect input */ > + MX6_PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL), > + /* SD2 write protect input */ > + MX6_PAD_SD4_DAT2__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL), > + /* Touchscreen IRQ */ > + MX6_PAD_SD4_DAT1__GPIO2_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL), > +}; > + > +static iomux_v3_cfg_t const misc_pads[] = { > + /* USB_OTG_ID = GPIO1_24*/ > + MX6_PAD_ENET_RX_ER__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL), > + /* H1 Power enable = GPIO1_0*/ > + MX6_PAD_GPIO_0__USB_H1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), > + /* OTG Power enable = GPIO4_15*/ > + MX6_PAD_KEY_ROW4__USB_OTG_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), > +}; > + > +iomux_v3_cfg_t const enet_pads[] = { > + MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), > + MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), > + MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), > + MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), > + MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), > + MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), > + MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), > + MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), > + MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), > + MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), > + MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), > + MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), > + MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), > + MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), > + MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), > +}; > + > +static void setup_iomux_enet(void) > +{ > + imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads)); > +} > + > +iomux_v3_cfg_t const usdhc1_pads[] = { > + MX6_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), > + MX6_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), > + MX6_PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), > + MX6_PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), > + MX6_PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), > + MX6_PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), > +}; > + > +iomux_v3_cfg_t const usdhc2_pads[] = { > + MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC2_PAD_CTRL), > + MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC2_PAD_CTRL), > + MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC2_PAD_CTRL), > + MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC2_PAD_CTRL), > + MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC2_PAD_CTRL), > + MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC2_PAD_CTRL), > + MX6_PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL), > +}; > + > +static iomux_v3_cfg_t const ecspi1_pads[] = { > + MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), > + MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), > + MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), > + MX6_PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(SPI_PAD_CTRL), > +}; > + > +iomux_v3_cfg_t const ecspi4_pads[] = { > + MX6_PAD_EIM_D21__ECSPI4_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), > + MX6_PAD_EIM_D22__ECSPI4_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), > + MX6_PAD_EIM_D28__ECSPI4_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), > + MX6_PAD_EIM_A25__GPIO5_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), > + MX6_PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL), > +}; > + > +/* only used for 4.3" display */ > +static iomux_v3_cfg_t const display_pads[] = { > + MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | MUX_PAD_CTRL(DISP_PAD_CTRL), > + MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15, > + MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02, > + MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03, > + MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00, > + MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01, > + MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02, > + MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03, > + MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04, > + MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05, > + MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06, > + MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07, > + MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08, > + MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09, > + MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10, > + MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11, > + MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12, > + MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13, > + MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14, > + MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15, > + MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16, > + MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17, > + MX6_PAD_DISP0_DAT18__IPU1_DISP0_DATA18, > + MX6_PAD_DISP0_DAT19__IPU1_DISP0_DATA19, > + MX6_PAD_DISP0_DAT20__IPU1_DISP0_DATA20, > + MX6_PAD_DISP0_DAT21__IPU1_DISP0_DATA21, > + MX6_PAD_DISP0_DAT22__IPU1_DISP0_DATA22, > + MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23, > +}; > + > +static iomux_v3_cfg_t const backlight_pads[] = { > + /* backlight PWM brightness control */ > + MX6_PAD_GPIO_9__PWM1_OUT | MUX_PAD_CTRL(NO_PAD_CTRL), > + /* backlight enable */ > + MX6_PAD_EIM_BCLK__GPIO6_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL), > + /* LCD power enable */ > + MX6_PAD_NANDF_CS2__GPIO6_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL), > +}; > + > +int board_spi_cs_gpio(unsigned bus, unsigned cs) > +{ > + if (bus == CONFIG_SF_DEFAULT_BUS && cs == CONFIG_SF_DEFAULT_CS) > + return IMX_GPIO_NR(5, 2); > + > + if (bus == 0 && cs == 0) > + return IMX_GPIO_NR(4, 9); > + > + return -1; > +} > + > +static void setup_spi(void) > +{ > + int i; > + > + imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads)); > + imx_iomux_v3_setup_multiple_pads(ecspi4_pads, ARRAY_SIZE(ecspi4_pads)); > + for (i = 0; i < 4; i++) > + enable_spi_clk(true, i); > + > + gpio_direction_output(ECSPI1_CS0, 1); > + gpio_direction_output(ECSPI4_CS1, 0); > + > + /* set cs0 to high (second device on spi bus #4) */ > + gpio_direction_output(ECSPI4_CS0, 1); > +} > + > +static void setup_iomux_gpio(void) > +{ > + imx_iomux_v3_setup_multiple_pads(gpio_pads, ARRAY_SIZE(gpio_pads)); > +} > + > +static void setup_iomux_uart(void) > +{ > + switch (CONFIG_MXC_UART_BASE) { > + case UART1_BASE: > + imx_iomux_v3_setup_multiple_pads(uart1_pads, > + ARRAY_SIZE(uart1_pads)); > + break; > + case UART2_BASE: > + imx_iomux_v3_setup_multiple_pads(uart2_pads, > + ARRAY_SIZE(uart2_pads)); > + break; > + case UART3_BASE: > + imx_iomux_v3_setup_multiple_pads(uart3_pads, > + ARRAY_SIZE(uart3_pads)); > + break; > + case UART4_BASE: > + imx_iomux_v3_setup_multiple_pads(uart4_pads, > + ARRAY_SIZE(uart4_pads)); > + break; > + } > +} > + > +#ifdef CONFIG_FSL_ESDHC > +struct fsl_esdhc_cfg usdhc_cfg[2] = { > + {USDHC1_BASE_ADDR}, > + {USDHC2_BASE_ADDR}, > +}; > + > +int board_mmc_getcd(struct mmc *mmc) > +{ > + return 1; > +} > + > +int board_mmc_init(bd_t *bis) > +{ > + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); > + imx_iomux_v3_setup_multiple_pads(usdhc1_pads, ARRAY_SIZE(usdhc1_pads)); > + > +#if defined(CONFIG_USE_SDHC2) > + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); > + imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); > + > + return fsl_esdhc_initialize(bis, &usdhc_cfg[0]) | > + fsl_esdhc_initialize(bis, &usdhc_cfg[1]); > +#else > + /* > + * usdhc2 has a levelshifter on the carrier board Rev. DV1, > + * that will automatically detect the driving direction. > + * During initialisation this isn't working correctly, > + * which causes DAT3 to be driven low towards the SD-card. > + * This causes a SD-card enetring the SPI-Mode > + * and therefore getting inaccessible until next power cycle. > + * As workaround we drive the DAT3 line as GPIO and set it high. > + * This makes usdhc2 unusable in u-boot, but works for the > + * initialisation in Linux > + */ > + imx_iomux_v3_setup_pad(MX6_PAD_SD2_DAT3__GPIO1_IO12 | > + MUX_PAD_CTRL(NO_PAD_CTRL)); > + gpio_direction_output(IMX_GPIO_NR(1, 12) , 1); > + > + return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); > +#endif > +} > +#endif > + > +/* > + * Do not overwrite the console > + * Use always serial for U-Boot console > + */ > +int overwrite_console(void) > +{ > + return 1; > +} > + > +int board_phy_config(struct phy_device *phydev) > +{ > +#if defined(CONFIG_PHY_MICREL_KSZ9031) Is there another possibly phy chip ? If not, can we get rid of the #ifdef ? > + /* control data pad skew - devaddr = 0x02, register = 0x04 */ > + ksz9031_phy_extended_write(phydev, 0x02, > + MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW, > + MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000); > + /* rx data pad skew - devaddr = 0x02, register = 0x05 */ > + ksz9031_phy_extended_write(phydev, 0x02, > + MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW, > + MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000); > + /* tx data pad skew - devaddr = 0x02, register = 0x06 */ > + ksz9031_phy_extended_write(phydev, 0x02, > + MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW, > + MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000); > + /* gtx and rx clock pad skew - devaddr = 0x02, register = 0x08 */ > + ksz9031_phy_extended_write(phydev, 0x02, > + MII_KSZ9031_EXT_RGMII_CLOCK_SKEW, > + MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x03FF); > +#endif /* CONFIG_PHY_MICREL_KSZ9031 */ > + > + if (phydev->drv->config) > + phydev->drv->config(phydev); > + > + > + > + return 0; > +} > + > +int board_eth_init(bd_t *bis) > +{ > + setup_iomux_enet(); > + return cpu_eth_init(bis); > +} > + > +#if defined(CONFIG_VIDEO_IPUV3) > + > +#if defined(CONFIG_VIDEO_BMP_LOGO) > +static int rotate_logo_one(unsigned char *out, unsigned char *in) > +{ > + int i, j; > + > + for (i = 0; i < BMP_LOGO_WIDTH; i++) > + for (j = 0; j < BMP_LOGO_HEIGHT; j++) > + out[j * BMP_LOGO_WIDTH + BMP_LOGO_HEIGHT - 1 - i] = > + in[i * BMP_LOGO_WIDTH + j]; > + return 0; > +} > + > +/* > + * Rotate the BMP_LOGO (only) > + * Will only work, if the logo is square, as > + * BMP_LOGO_HEIGHT and BMP_LOGO_WIDTH are defines, not variables > + */ > +void rotate_logo(int rotations) > +{ > + unsigned char out_logo[BMP_LOGO_WIDTH * BMP_LOGO_HEIGHT]; > + unsigned char *in_logo; > + int i, j; > + > + if (BMP_LOGO_WIDTH != BMP_LOGO_HEIGHT) > + return; > + > + in_logo = bmp_logo_bitmap; > + > + /* one 90 degree rotation */ > + if (rotations == 1 || rotations == 2 || rotations == 3) > + rotate_logo_one(out_logo, in_logo); > + > + /* second 90 degree rotation */ > + if (rotations == 2 || rotations == 3) > + rotate_logo_one(in_logo, out_logo); > + > + /* third 90 degree rotation */ > + if (rotations == 3) > + rotate_logo_one(out_logo, in_logo); > + > + /* copy result back to original array */ > + if (rotations == 1 || rotations == 3) > + for (i = 0; i < BMP_LOGO_WIDTH; i++) > + for (j = 0; j < BMP_LOGO_HEIGHT; j++) > + in_logo[i * BMP_LOGO_WIDTH + j] = > + out_logo[i * BMP_LOGO_WIDTH + j]; > +} > +#endif Should we put this code in a more common location ? As candidate I see common/lcd_console_rotation.c or drivers/video/cfb_console.c > + > +static void enable_display_power(void) > +{ > + imx_iomux_v3_setup_multiple_pads(backlight_pads, > + ARRAY_SIZE(backlight_pads)); > + > + /* backlight enable */ > + gpio_direction_output(IMX_GPIO_NR(6, 31), 1); > + /* LCD power enable */ > + gpio_direction_output(IMX_GPIO_NR(6, 15), 1); > + > + /* enable backlight PWM 1 */ > + if (pwm_init(0, 0, 0)) > + goto error; > + /* duty cycle 500ns, period: 3000ns */ > + if (pwm_config(0, 50000, 300000)) > + goto error; > + if (pwm_enable(0)) > + goto error; > + return; > + > +error: > + puts("error init pwm for backlight\n"); > + return; > +} > + > +static void enable_lvds(struct display_info_t const *dev) > +{ > + struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; > + struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; > + int reg; > + s32 timeout = 100000; > + > + /* set PLL5 clock */ > + reg = readl(&ccm->analog_pll_video); > + reg |= BM_ANADIG_PLL_VIDEO_POWERDOWN; > + writel(reg, &ccm->analog_pll_video); > + > + /* set PLL5 to 232720000Hz */ > + reg &= ~BM_ANADIG_PLL_VIDEO_DIV_SELECT; > + reg |= BF_ANADIG_PLL_VIDEO_DIV_SELECT(0x26); > + reg &= ~BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT; > + reg |= BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0); > + writel(reg, &ccm->analog_pll_video); > + > + writel(BF_ANADIG_PLL_VIDEO_NUM_A(0xC0238), > + &ccm->analog_pll_video_num); > + writel(BF_ANADIG_PLL_VIDEO_DENOM_B(0xF4240), > + &ccm->analog_pll_video_denom); > + > + reg &= ~BM_ANADIG_PLL_VIDEO_POWERDOWN; > + writel(reg, &ccm->analog_pll_video); > + > + while (timeout--) > + if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK) > + break; > + if (timeout < 0) > + printf("Warning: video pll lock timeout!\n"); > + > + reg = readl(&ccm->analog_pll_video); > + reg |= BM_ANADIG_PLL_VIDEO_ENABLE; > + reg &= ~BM_ANADIG_PLL_VIDEO_BYPASS; > + writel(reg, &ccm->analog_pll_video); > + > + /* set LDB0, LDB1 clk select to 000/000 (PLL5 clock) */ > + reg = readl(&ccm->cs2cdr); > + reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK > + | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK); > + reg |= (0 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) > + | (0 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET); > + writel(reg, &ccm->cs2cdr); > + > + reg = readl(&ccm->cscmr2); > + reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV; > + writel(reg, &ccm->cscmr2); > + > + reg = readl(&ccm->chsccdr); > + reg |= (CHSCCDR_CLK_SEL_LDB_DI0 > + << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET); > + writel(reg, &ccm->chsccdr); > + > + reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES > + | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH > + | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_HIGH > + | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG > + | IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT > + | IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED > + | IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0; > + writel(reg, &iomux->gpr[2]); > + > + reg = readl(&iomux->gpr[3]); > + reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK) > + | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 > + << IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET); > + writel(reg, &iomux->gpr[3]); > + > + return; > +} > + > +static void enable_spi(struct display_info_t const *dev) > +{ Names are just a little confusing. There is a setup_spi and enable_spi, and it takes a bit to understand that enable_spi is only for display. You could rename enable_spi with a name related to video/display. > + struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; > + struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; > + int reg; > + s32 timeout = 100000; > + > +#if defined(CONFIG_VIDEO_BMP_LOGO) > + rotate_logo(3); /* portrait display in landscape mode */ > +#endif > + > + lgdisplay = 1; > + ipu_set_ldb_clock(28341000); Where is coming from this value ? Can you add a comment for it ? > + > + reg = readl(&ccm->cs2cdr); > + > + /* select pll 5 clock */ > + reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK > + | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK); > + writel(reg, &ccm->cs2cdr); > + > + /* set PLL5 to 197994996Hz */ > + reg &= ~BM_ANADIG_PLL_VIDEO_DIV_SELECT; > + reg |= BF_ANADIG_PLL_VIDEO_DIV_SELECT(0x21); > + reg &= ~BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT; > + reg |= BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0); > + writel(reg, &ccm->analog_pll_video); > + > + writel(BF_ANADIG_PLL_VIDEO_NUM_A(0xfbf4), > + &ccm->analog_pll_video_num); > + writel(BF_ANADIG_PLL_VIDEO_DENOM_B(0xf4240), > + &ccm->analog_pll_video_denom); > + > + reg &= ~BM_ANADIG_PLL_VIDEO_POWERDOWN; > + writel(reg, &ccm->analog_pll_video); > + > + while (timeout--) > + if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK) > + break; > + if (timeout < 0) > + printf("Warning: video pll lock timeout!\n"); > + > + reg = readl(&ccm->analog_pll_video); > + reg |= BM_ANADIG_PLL_VIDEO_ENABLE; > + reg &= ~BM_ANADIG_PLL_VIDEO_BYPASS; > + writel(reg, &ccm->analog_pll_video); > + > + /* set LDB0, LDB1 clk select to 000/000 (PLL5 clock) */ > + reg = readl(&ccm->cs2cdr); > + reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK > + | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK); > + reg |= (0 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) > + | (0 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET); > + writel(reg, &ccm->cs2cdr); > + > + reg = readl(&ccm->cscmr2); > + reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV; > + writel(reg, &ccm->cscmr2); > + > + reg = readl(&ccm->chsccdr); > + reg |= (CHSCCDR_CLK_SEL_LDB_DI0 > + << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET); > + reg &= ~MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK; > + reg |= (2 << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET); > + reg &= ~MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK; > + reg |= (2 << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET); > + writel(reg, &ccm->chsccdr); > + > + reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES > + | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH > + | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_HIGH > + | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG > + | IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT > + | IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED > + | IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0; > + writel(reg, &iomux->gpr[2]); > + > + reg = readl(&iomux->gpr[3]); > + reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK) > + | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 > + << IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET); > + writel(reg, &iomux->gpr[3]); > + > + imx_iomux_v3_setup_multiple_pads( > + display_pads, > + ARRAY_SIZE(display_pads)); > + > + return; > +} > + > +struct display_info_t const displays[] = {{ > + .bus = -1, > + .addr = 0, > + .pixfmt = IPU_PIX_FMT_RGB24, > + .detect = NULL, > + .enable = enable_lvds, > + .mode = { > + .name = "lb07wv8", > + .refresh = 60, > + .xres = 800, > + .yres = 480, > + .pixclock = 30066, > + .left_margin = 88, > + .right_margin = 88, > + .upper_margin = 20, > + .lower_margin = 20, > + .hsync_len = 80, > + .vsync_len = 5, > + .sync = FB_SYNC_EXT, > + .vmode = FB_VMODE_NONINTERLACED > +} }, { > + .bus = -1, > + .addr = 0, > + .pixfmt = IPU_PIX_FMT_RGB24, > + .detect = NULL, > + .enable = enable_spi, > + .mode = { > + .name = "lg4573", > + .refresh = 57, > + .xres = 480, > + .yres = 800, > + .pixclock = 37037, > + .left_margin = 59, > + .right_margin = 10, > + .upper_margin = 15, > + .lower_margin = 15, > + .hsync_len = 10, > + .vsync_len = 15, > + .sync = FB_SYNC_EXT | FB_SYNC_HOR_HIGH_ACT | > + FB_SYNC_VERT_HIGH_ACT, > + .vmode = FB_VMODE_NONINTERLACED > +} } }; > +size_t display_count = ARRAY_SIZE(displays); > + > +static void setup_display(void) > +{ > + enable_ipu_clock(); > + enable_display_power(); > +} > + > +/* no console on this board */ > +int board_cfb_skip(void) > +{ > + return 1; > +} > +#endif > + > +int board_early_init_f(void) > +{ > + setup_iomux_uart(); > + setup_iomux_gpio(); > + > + gpio_direction_output(SOFT_RESET_GPIO, 1); > + gpio_direction_output(SD2_DRIVER_ENABLE, 1); > + > +#if defined(CONFIG_VIDEO_IPUV3) > + setup_display(); > +#endif > + return 0; > +} > + > +iomux_v3_cfg_t nfc_pads[] = { > + MX6_PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NO_PAD_CTRL), > + MX6_PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NO_PAD_CTRL), > + MX6_PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(NO_PAD_CTRL), > + MX6_PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL), > + MX6_PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NO_PAD_CTRL), > + MX6_PAD_NANDF_CS1__NAND_CE1_B | MUX_PAD_CTRL(NO_PAD_CTRL), > + MX6_PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NO_PAD_CTRL), > + MX6_PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NO_PAD_CTRL), > + MX6_PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL), > + MX6_PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL), > + MX6_PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL), > + MX6_PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL), > + MX6_PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL), > + MX6_PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL), > + MX6_PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL), > + MX6_PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL), > + MX6_PAD_SD4_DAT0__NAND_DQS | MUX_PAD_CTRL(NO_PAD_CTRL), > +}; > + > +static void setup_gpmi_nand(void) > +{ > + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; > + > + /* config gpmi nand iomux */ > + imx_iomux_v3_setup_multiple_pads(nfc_pads, > + ARRAY_SIZE(nfc_pads)); > + > + /* gate ENFC_CLK_ROOT clock first,before clk source switch */ > + clrbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK); > + > + /* config gpmi and bch clock to 100 MHz */ > + clrsetbits_le32(&mxc_ccm->cs2cdr, > + MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK | > + MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK | > + MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK, > + MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) | > + MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) | > + MXC_CCM_CS2CDR_ENFC_CLK_SEL(3)); > + > + /* enable ENFC_CLK_ROOT clock */ > + setbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK); > + > + /* enable gpmi and bch clock gating */ > + setbits_le32(&mxc_ccm->CCGR4, > + MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK | > + MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK | > + MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK | > + MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK | > + MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET); > + > + /* enable apbh clock gating */ > + setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK); > +} > + > +int board_init(void) > +{ > + struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; > + > + /* address of boot parameters */ > + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; > + > + setup_spi(); > + > + setup_i2c(0, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, > + &i2c_pad_info1); > + setup_i2c(1, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, > + &i2c_pad_info2); > + setup_i2c(2, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, > + &i2c_pad_info3); > + setup_i2c(3, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, > + &i2c_pad_info4); > + > + /* SPI NOR Flash read only */ > + gpio_request(CONFIG_GPIO_ENABLE_SPI_FLASH, "ena_spi_nor"); > + gpio_direction_output(CONFIG_GPIO_ENABLE_SPI_FLASH, 0); > + gpio_free(CONFIG_GPIO_ENABLE_SPI_FLASH); > + > + /* enable all LEDs */ > + gpio_request(IMX_GPIO_NR(2, 13), "LED ena"); /* 25 */ > + gpio_direction_output(IMX_GPIO_NR(1, 25), 0); > + > + /* switch off Status LEDs */ > + gpio_request(IMX_GPIO_NR(6, 16), "LED yellow"); /* 176 */ > + gpio_direction_output(IMX_GPIO_NR(6, 16), 1); > + gpio_request(IMX_GPIO_NR(2, 28), "LED red"); /* 60 */ > + gpio_direction_output(IMX_GPIO_NR(2, 28), 1); > + gpio_request(IMX_GPIO_NR(5, 4), "LED green"); /* 132 */ > + gpio_direction_output(IMX_GPIO_NR(5, 4), 1); > + gpio_request(IMX_GPIO_NR(2, 29), "LED blue"); /* 61 */ > + gpio_direction_output(IMX_GPIO_NR(2, 29), 1); > + > + setup_gpmi_nand(); > + > + /* ENET_RX_ER for USB_OTG_ID */ > + clrsetbits_le32(&iomux->gpr[1], IOMUXC_GPR1_USB_OTG_ID_SEL_MASK, 0); > + imx_iomux_v3_setup_multiple_pads(misc_pads, ARRAY_SIZE(misc_pads)); > + > + /* enable spi bus #2 SS drivers */ > + gpio_direction_output(IMX_GPIO_NR(6, 6), 1); > + > + return 0; > +} > + > +int board_late_init(void) > +{ > + char *my_bootdelay; > + char bootmode = 0; > + > + /* > + * Check the boot-source. If booting from NOR Flash, > + * disable bootdelay > + */ > + gpio_request(IMX_GPIO_NR(7, 6), "bootsel0"); > + gpio_direction_input(IMX_GPIO_NR(7, 6)); > + gpio_request(IMX_GPIO_NR(7, 7), "bootsel1"); > + gpio_direction_input(IMX_GPIO_NR(7, 7)); > + gpio_request(IMX_GPIO_NR(7, 1), "bootsel2"); > + gpio_direction_input(IMX_GPIO_NR(7, 1)); > + bootmode |= (gpio_get_value(IMX_GPIO_NR(7, 6)) ? 1 : 0) << 0; > + bootmode |= (gpio_get_value(IMX_GPIO_NR(7, 7)) ? 1 : 0) << 1; > + bootmode |= (gpio_get_value(IMX_GPIO_NR(7, 1)) ? 1 : 0) << 2; > + > + if (bootmode == 7) { > + my_bootdelay = getenv("nor_bootdelay"); > + if (my_bootdelay != NULL) > + setenv("bootdelay", my_bootdelay); > + else > + setenv("bootdelay", "-2"); > + } > + > + if (lgdisplay) > + lg4573_spi_startup(0, 0, 10000000, SPI_MODE_0); > + > + return 0; > +} > + > +int checkboard(void) > +{ > + puts("Board: aristaitenos2\n"); > + return 0; > +} > + > +#ifdef CONFIG_USB_EHCI_MX6 > +int board_ehci_hcd_init(int port) > +{ > + int ret; > + > + ret = gpio_request(ARISTAINETOS2_USB_H1_PWR, "usb-h1-pwr"); > + if (!ret) > + gpio_direction_output(ARISTAINETOS2_USB_H1_PWR, 1); > + ret = gpio_request(ARISTAINETOS2_USB_OTG_PWR, "usb-OTG-pwr"); > + if (!ret) > + gpio_direction_output(ARISTAINETOS2_USB_OTG_PWR, 1); > + return 0; > +} > + > +int board_ehci_power(int port, int on) > +{ > + if (port) > + gpio_set_value(ARISTAINETOS2_USB_OTG_PWR, on); > + else > + gpio_set_value(ARISTAINETOS2_USB_H1_PWR, on); > + return 0; > +} > +#endif > diff --git a/board/aristainetos2/aristainetos2.cfg > b/board/aristainetos2/aristainetos2.cfg > new file mode 100644 > index 0000000..a66bc1c > --- /dev/null > +++ b/board/aristainetos2/aristainetos2.cfg > @@ -0,0 +1,34 @@ > +/* > + * (C) Copyright 2014 > + * Heiko Schocher, DENX Software Engineering, h...@denx.de. > + * > + * Based on: > + * Copyright (C) 2013 Boundary Devices > + * > + * SPDX-License-Identifier: GPL-2.0+ > + * > + * Refer doc/README.imximage for more details about how-to configure > + * and create imximage boot image > + * > + * The syntax is taken as close as possible with the kwbimage > + */ > + > +/* image version */ > +IMAGE_VERSION 2 > + > +/* > + * Boot Device : one of > + * spi, sd > + */ > +BOOT_FROM spi > + > +#define __ASSEMBLY__ > +#include <config.h> > +#include "asm/arch/mx6-ddr.h" > +#include "asm/arch/iomux.h" > +#include "asm/arch/crm_regs.h" > + > +#include "ddr-setup.cfg" > +#include "nt5cc256m16cp.cfg" > +#include "clocks.cfg" > +#include "axi.cfg" > diff --git a/board/aristainetos2/axi.cfg b/board/aristainetos2/axi.cfg > new file mode 100644 > index 0000000..0bb816c > --- /dev/null > +++ b/board/aristainetos2/axi.cfg > @@ -0,0 +1,22 @@ > +/* > + * Copyright (C) 2013 Boundary Devices > + * > + * SPDX-License-Identifier: GPL-2.0+ > + * > + * Device Configuration Data (DCD) > + * > + * Each entry must have the format: > + * Addr-type Address Value > + * > + * where: > + * Addr-type register length (1,2 or 4 bytes) > + * Address absolute address of the register > + * value value to be stored in the register > + */ > + > +/* enable AXI cache for VDOA/VPU/IPU */ > +DATA 4, MX6_IOMUXC_GPR4, 0xF00000CF > + > +/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ > +DATA 4, MX6_IOMUXC_GPR6, 0x007F007F > +DATA 4, MX6_IOMUXC_GPR7, 0x007F007F > diff --git a/board/aristainetos2/clocks.cfg b/board/aristainetos2/clocks.cfg > new file mode 100644 > index 0000000..987d9a4 > --- /dev/null > +++ b/board/aristainetos2/clocks.cfg > @@ -0,0 +1,24 @@ > +/* > + * Copyright (C) 2013 Boundary Devices > + * > + * SPDX-License-Identifier: GPL-2.0+ > + * > + * Device Configuration Data (DCD) > + * > + * Each entry must have the format: > + * Addr-type Address Value > + * > + * where: > + * Addr-type register length (1,2 or 4 bytes) > + * Address absolute address of the register > + * value value to be stored in the register > + */ > + > +/* set the default clock gate to save power */ > +DATA 4, CCM_CCGR0, 0x00c03f3f > +DATA 4, CCM_CCGR1, 0x0030fcff > +DATA 4, CCM_CCGR2, 0x0fffcfc0 > +DATA 4, CCM_CCGR3, 0x3ff0300f > +DATA 4, CCM_CCGR4, 0xfffff300 > +DATA 4, CCM_CCGR5, 0x0f0000c3 > +DATA 4, CCM_CCGR6, 0x00000fff > diff --git a/board/aristainetos2/ddr-setup.cfg > b/board/aristainetos2/ddr-setup.cfg > new file mode 100644 > index 0000000..3d5d894 > --- /dev/null > +++ b/board/aristainetos2/ddr-setup.cfg > @@ -0,0 +1,59 @@ > +/* > + * Copyright (C) 2013 Boundary Devices > + * > + * SPDX-License-Identifier: GPL-2.0+ > + * > + * Device Configuration Data (DCD) > + * > + * Each entry must have the format: > + * Addr-type Address Value > + * > + * where: > + * Addr-type register length (1,2 or 4 bytes) > + * Address absolute address of the register > + * value value to be stored in the register > + */ > + > +/* DDR IO TYPE */ > +DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000 > +DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000 > +/* Clock */ > +DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00000030 > +DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00000030 > +/* Address */ > +DATA 4, MX6_IOM_DRAM_CAS, 0x00000030 > +DATA 4, MX6_IOM_DRAM_RAS, 0x00000030 > +DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030 > +/* Control */ > +DATA 4, MX6_IOM_DRAM_RESET, 0x00000030 > +DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000 > +DATA 4, MX6_IOM_DRAM_SDODT0, 0x00000030 > +DATA 4, MX6_IOM_DRAM_SDODT1, 0x00000030 > +DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030 > +/* Data Strobe */ > +DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000 > +DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000028 > +DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000028 > +DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000028 > +DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000028 > +DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000028 > +DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000028 > +DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000028 > +DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000028 > +DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000 > +DATA 4, MX6_IOM_GRP_B0DS, 0x00000028 > +DATA 4, MX6_IOM_GRP_B1DS, 0x00000028 > +DATA 4, MX6_IOM_GRP_B2DS, 0x00000028 > +DATA 4, MX6_IOM_GRP_B3DS, 0x00000028 > +DATA 4, MX6_IOM_GRP_B4DS, 0x00000028 > +DATA 4, MX6_IOM_GRP_B5DS, 0x00000028 > +DATA 4, MX6_IOM_GRP_B6DS, 0x00000028 > +DATA 4, MX6_IOM_GRP_B7DS, 0x00000028 > +DATA 4, MX6_IOM_DRAM_DQM0, 0x00000028 > +DATA 4, MX6_IOM_DRAM_DQM1, 0x00000028 > +DATA 4, MX6_IOM_DRAM_DQM2, 0x00000028 > +DATA 4, MX6_IOM_DRAM_DQM3, 0x00000028 > +DATA 4, MX6_IOM_DRAM_DQM4, 0x00000028 > +DATA 4, MX6_IOM_DRAM_DQM5, 0x00000028 > +DATA 4, MX6_IOM_DRAM_DQM6, 0x00000028 > +DATA 4, MX6_IOM_DRAM_DQM7, 0x00000028 > diff --git a/board/aristainetos2/nt5cc256m16cp.cfg > b/board/aristainetos2/nt5cc256m16cp.cfg > new file mode 100644 > index 0000000..2ff41e9 > --- /dev/null > +++ b/board/aristainetos2/nt5cc256m16cp.cfg > @@ -0,0 +1,60 @@ > +/* > + * Copyright (C) 2013 Boundary Devices > + * > + * SPDX-License-Identifier: GPL-2.0+ > + */ > +/* ZQ Calibration */ > +DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xa1390003 > +DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x001F001F > +DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x001F001F > +DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x001F001F > +DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x001F001F > +/* > + * DQS gating, read delay, write delay calibration values > + */ > +DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x42190217 > +DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x017B017B > +DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x4176017B > +DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x015F016C > +DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x4C4C4D4C > +DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x4A4D4C48 > +DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x3F3F3F40 > +DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x3538382E > +/* read data bit delay */ > +DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333 > +DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333 > +DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333 > +DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333 > +DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333 > +DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333 > +DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333 > +DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333 > +/* Complete calibration by forced measurment */ > +DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800 > +DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800 > +/* in DDR3, 64-bit mode, only MMDC0 is initiated */ > +DATA 4, MX6_MMDC_P0_MDPDC, 0x00020025 > +DATA 4, MX6_MMDC_P0_MDOTC, 0x00333030 > +DATA 4, MX6_MMDC_P0_MDCFG0, 0x676B5313 > +DATA 4, MX6_MMDC_P0_MDCFG1, 0xB66E8B63 > +DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB > +DATA 4, MX6_MMDC_P0_MDMISC, 0x00001740 > +DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000 > +DATA 4, MX6_MMDC_P0_MDRWD, 0x000026d2 > +DATA 4, MX6_MMDC_P0_MDOR, 0x006B1023 > +DATA 4, MX6_MMDC_P0_MDASP, 0x00000027 > +DATA 4, MX6_MMDC_P0_MDCTL, 0x84190000 > + > +DATA 4, MX6_MMDC_P0_MDSCR, 0x04008032 > +DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033 > +DATA 4, MX6_MMDC_P0_MDSCR, 0x00048031 > +DATA 4, MX6_MMDC_P0_MDSCR, 0x05208030 > +DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040 > + > +/* final ddr setup */ > +DATA 4, MX6_MMDC_P0_MDREF, 0x00005800 > +DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00011117 > +DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00011117 > +DATA 4, MX6_MMDC_P0_MDPDC, 0x00025565 > +DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006 > +DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000 > diff --git a/configs/aristainetos2_defconfig b/configs/aristainetos2_defconfig > new file mode 100644 > index 0000000..26292fd > --- /dev/null > +++ b/configs/aristainetos2_defconfig > @@ -0,0 +1,3 @@ > +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/aristainetos2/aristainetos2.cfg,MX6DL" > +CONFIG_ARM=y > +CONFIG_TARGET_ARISTAINETOS2=y > diff --git a/include/configs/aristainetos2.h b/include/configs/aristainetos2.h > new file mode 100644 > index 0000000..0294359 > --- /dev/null > +++ b/include/configs/aristainetos2.h > @@ -0,0 +1,351 @@ > +/* > + * (C) Copyright 2015 > + * Heiko Schocher, DENX Software Engineering, h...@denx.de. > + * > + * Based on: > + * Copyright (C) 2012 Freescale Semiconductor, Inc. > + * > + * Configuration settings for the Freescale i.MX6DL aristainetos2 board. > + * > + * SPDX-License-Identifier: GPL-2.0+ > + */ > +#ifndef __ARISTAINETOS2_CONFIG_H > +#define __ARISTAINETOS2_CONFIG_H > + > +#define CONFIG_MX6 > + > +#include "mx6_common.h" > +#include <linux/sizes.h> > + > +#define CONFIG_DISPLAY_CPUINFO > +#define CONFIG_DISPLAY_BOARDINFO > + > +#include <asm/arch/imx-regs.h> > +#include <asm/imx-common/gpio.h> > + > +#define CONFIG_MACH_TYPE 4501 > +#define CONFIG_MMCROOT "/dev/mmcblk0p1" > +#define CONFIG_HOSTNAME aristainetos2 > +#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024) > + > +#define CONFIG_SYS_GENERIC_BOARD > + > +/* Size of malloc() pool */ > +#define CONFIG_SYS_MALLOC_LEN (64 * SZ_1M) > + > +#define CONFIG_BOARD_EARLY_INIT_F > +#define CONFIG_BOARD_LATE_INIT > +#define CONFIG_MXC_GPIO > + > +#define CONFIG_MXC_UART > +#define CONFIG_MXC_UART_BASE UART2_BASE > +#define CONFIG_CONSOLE_DEV "ttymxc1" > + > +#define CONFIG_CMD_FUSE > +#define CONFIG_MXC_OCOTP > + > +/* MMC Configs */ > +#define CONFIG_FSL_ESDHC > +#define CONFIG_FSL_USDHC > +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 > + > +#define CONFIG_MMC > +#define CONFIG_CMD_MMC > +#define CONFIG_GENERIC_MMC > +#define CONFIG_BOUNCE_BUFFER > +#define CONFIG_CMD_EXT2 > +#define CONFIG_CMD_FAT > +#define CONFIG_DOS_PARTITION > + > +#define CONFIG_CMD_PING > +#define CONFIG_CMD_DHCP > +#define CONFIG_CMD_MII > +#define CONFIG_CMD_NET > +#define CONFIG_FEC_MXC > +#define CONFIG_MII > +#define IMX_FEC_BASE ENET_BASE_ADDR > +#define CONFIG_FEC_XCV_TYPE RGMII > +#define CONFIG_ETHPRIME "FEC" > +#define CONFIG_FEC_MXC_PHYADDR 0 > +#define CONFIG_PHYLIB > +#define CONFIG_PHY_MICREL > +#define CONFIG_PHY_MICREL_KSZ9031 > + > +#define CONFIG_CMD_SF > +#define CONFIG_SPI_FLASH > +#define CONFIG_SPI_FLASH_MTD > +#define CONFIG_SPI_FLASH_STMICRO > +#define CONFIG_MXC_SPI > +#define CONFIG_SF_DEFAULT_BUS 3 > +#define CONFIG_SF_DEFAULT_CS 1 > +#define CONFIG_SF_DEFAULT_SPEED 20000000 > +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 > +#define CONFIG_SYS_SPI_ST_ENABLE_WP_PIN > + > +/* allow to overwrite serial and ethaddr */ > +#define CONFIG_ENV_OVERWRITE > +#define CONFIG_CONS_INDEX 1 > +#define CONFIG_BAUDRATE 115200 > + > +/* Command definition */ > +#include <config_cmd_default.h> > + > +#define CONFIG_CMD_BMODE > +#define CONFIG_CMD_BOOTZ > +#define CONFIG_CMD_SETEXPR > +#undef CONFIG_CMD_IMLS > + > +#define CONFIG_BOOTDELAY 3 > + > +#define CONFIG_LOADADDR 0x12000000 > +#define CONFIG_SYS_TEXT_BASE 0x17800000 > + > +#define CONFIG_EXTRA_ENV_SETTINGS \ > + "script=u-boot.scr\0" \ > + "fit_file=/boot/system.itb\0" \ > + "loadaddr=0x12000000\0" \ > + "fit_addr_r=0x14000000\0" \ > + "uboot=/boot/u-boot.imx\0" \ > + "uboot_sz=d0000\0" \ > + "rescue_sys_addr=f0000\0" \ > + "rescue_sys_length=f10000\0" \ > + "board_type=aristainetos2_7@1\0" \ > + "panel=lb07wv8\0" \ > + "splashpos=m,m\0" \ > + "console=" CONFIG_CONSOLE_DEV "\0" \ > + "nor_bootdelay=-2\0" \ > + "fdt_high=0xffffffff\0" \ > + "initrd_high=0xffffffff\0" \ > + "mtdids=nand0=gpmi-nand,nor0=spi3.1\0" \ > + "mtdparts=mtdparts=spi3.1:832k(u-boot),64k(env),64k(env-red)," \ > + "-(rescue-system);gpmi-nand:-(ubi)\0" \ > + "addmisc=setenv bootargs ${bootargs} net.ifnames=0 consoleblank=0\0" \ > + "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ > + "set_fit_default=fdt addr ${fit_addr_r};fdt set /configurations " \ > + "default ${board_type}\0" \ > + "get_env=mw ${loadaddr} 0 0x20000;" \ > + "mmc rescan;" \ > + "ext2load mmc ${mmcdev}:${mmcpart} ${loadaddr} env.txt;" \ > + "env import -t ${loadaddr}\0" \ > + "default_env=mw ${loadaddr} 0 0x20000;" \ > + "env export -t ${loadaddr} serial# ethaddr eth1addr " \ > + "board_type panel;" \ > + "env default -a;" \ > + "env import -t ${loadaddr}\0" \ > + "loadbootscript=" \ > + "ext2load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ > + "bootscript=echo Running bootscript from mmc ...; " \ > + "source\0" \ > + "mmcpart=1\0" \ > + "mmcdev=0\0" \ > + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ > + "mmcargs=setenv bootargs console=${console},${baudrate} " \ > + "root=${mmcroot}\0" \ > + "mmcboot=echo Booting from mmc ...; " \ > + "run mmcargs addmtd addmisc set_fit_default;" \ > + "bootm ${fit_addr_r}\0" \ > + "mmc_load_fit=ext2load mmc ${mmcdev}:${mmcpart} ${fit_addr_r} " \ > + "${fit_file}\0" \ > + "mmc_load_uboot=ext2load mmc ${mmcdev}:${mmcpart} ${loadaddr} " \ > + "${uboot}\0" \ > + "mmc_upd_uboot=mw.b ${loadaddr} 0xff ${uboot_sz};" \ > + "setexpr cmp_buf ${loadaddr} + ${uboot_sz};" \ > + "setexpr uboot_maxsize ${uboot_sz} - 400;" \ > + "mw.b ${cmp_buf} 0x00 ${uboot_sz};" \ > + "run mmc_load_uboot;sf probe;sf erase 0 ${uboot_sz};" \ > + "sf write ${loadaddr} 400 ${filesize};" \ > + "sf read ${cmp_buf} 400 ${uboot_sz};" \ > + "cmp.b ${loadaddr} ${cmp_buf} ${uboot_maxsize}\0" \ > + "ubiargs=setenv bootargs console=${console},${baudrate} " \ > + "ubi.mtd=0,4096 root=ubi0:rootfs rootfstype=ubifs\0 " \ > + "ubiboot=echo Booting from ubi ...; " \ > + "run ubiargs addmtd addmisc set_fit_default;" \ > + "bootm ${fit_addr_r}\0" \ > + "ubifs_load_fit=sf probe;ubi part ubi 4096;ubifsmount ubi:rootfs;" \ > + "ubifsload ${fit_addr_r} /boot/system.itb; " \ > + "imi ${fit_addr_r}\0 " \ > + "rescueargs=setenv bootargs console=${console},${baudrate} " \ > + "root=/dev/ram rw\0 " \ > + "rescueboot=echo Booting rescue system from NOR ...; " \ > + "run rescueargs addmtd addmisc set_fit_default;" \ > + "bootm ${fit_addr_r}\0" \ > + "rescue_load_fit=sf probe;sf read ${fit_addr_r} ${rescue_sys_addr} " \ > + "${rescue_sys_length}; imi ${fit_addr_r}\0 " > + > + > +#define CONFIG_BOOTCOMMAND \ > + "mmc dev ${mmcdev};" \ > + "if mmc rescan; then " \ > + "if run loadbootscript; then " \ > + "run bootscript; " \ > + "else " \ > + "if run mmc_load_fit; then " \ > + "run mmcboot; " \ > + "else " \ > + "if run ubifs_load_fit; then " \ > + "run ubiboot; " \ > + "else " \ > + "if run rescue_load_fit; then " \ > + "run rescueboot; " \ > + "else " \ > + "echo RESCUE SYSTEM BOOT " \ > + "FAILURE;" \ > + "fi; " \ > + "fi; " \ > + "fi; " \ > + "fi; " \ > + "else " \ > + "if run ubifs_load_fit; then " \ > + "run ubiboot; " \ > + "else " \ > + "if run rescue_load_fit; then " \ > + "run rescueboot; " \ > + "else " \ > + "echo RESCUE SYSTEM BOOT FAILURE;" \ > + "fi; " \ > + "fi; " \ > + "fi" > + > +#define CONFIG_ARP_TIMEOUT 200UL > + > +/* Miscellaneous configurable options */ > +#define CONFIG_SYS_LONGHELP > +#define CONFIG_SYS_HUSH_PARSER > +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " > +#define CONFIG_AUTO_COMPLETE > +#define CONFIG_SYS_CBSIZE 256 > + > +/* Print Buffer Size */ > +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + > 16) > +#define CONFIG_SYS_MAXARGS 16 > +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE > + > +#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM > +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + > 0x100000) > +#define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000 > + > +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR > + > +#define CONFIG_CMDLINE_EDITING > +#define CONFIG_STACKSIZE (128 * 1024) > + > +/* Physical Memory Map */ > +#define CONFIG_NR_DRAM_BANKS 1 > +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR > + > +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM > +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR > +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE > + > +#define CONFIG_SYS_INIT_SP_OFFSET \ > + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) > +#define CONFIG_SYS_INIT_SP_ADDR \ > + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) > + > +/* FLASH and environment organization */ > +#define CONFIG_SYS_NO_FLASH > + > +#define CONFIG_ENV_SIZE (12 * 1024) > +#define CONFIG_ENV_IS_IN_SPI_FLASH > +#define CONFIG_SYS_REDUNDAND_ENVIRONMENT > +#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS > +#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS > +#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED > +#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE > +#define CONFIG_ENV_SECT_SIZE (0x010000) > +#define CONFIG_ENV_OFFSET (0x0d0000) > +#define CONFIG_ENV_OFFSET_REDUND (0x0e0000) > + > +#define CONFIG_OF_LIBFDT > + > +#define CONFIG_CMD_CACHE > + > +#define CONFIG_SYS_FSL_USDHC_NUM 2 > + > +#define CONFIG_CMD_I2C > +#define CONFIG_SYS_I2C > +#define CONFIG_SYS_I2C_MXC > +#define CONFIG_SYS_I2C_SPEED 100000 > +#define CONFIG_SYS_I2C_SLAVE 0x7f > +#define CONFIG_SYS_I2C_NOPROBES { {0, 0x00} } > +#define CONFIG_SYS_NUM_I2C_ADAPTERS 4 > + > +#define CONFIG_CMD_GPIO > +#define CONFIG_GPIO_ENABLE_SPI_FLASH IMX_GPIO_NR(2, 15) > + > +/* NAND stuff */ > +#define CONFIG_CMD_NAND > +#define CONFIG_CMD_NAND_TRIMFFS > +#define CONFIG_NAND_MXS > +#define CONFIG_SYS_MAX_NAND_DEVICE 1 > +#define CONFIG_SYS_NAND_BASE 0x40000000 > +#define CONFIG_SYS_NAND_5_ADDR_CYCLE > +#define CONFIG_SYS_NAND_ONFI_DETECTION > + > +/* DMA stuff, needed for GPMI/MXS NAND support */ > +#define CONFIG_APBH_DMA > +#define CONFIG_APBH_DMA_BURST > +#define CONFIG_APBH_DMA_BURST8 > + > +/* RTC */ > +#define CONFIG_SYS_I2C_RTC_ADDR 0x68 > +#define CONFIG_SYS_RTC_BUS_NUM 2 > +#define CONFIG_RTC_M41T11 > +#define CONFIG_CMD_DATE > + > +/* USB Configs */ > +#define CONFIG_CMD_USB > +#define CONFIG_CMD_FAT > +#define CONFIG_USB_EHCI > +#define CONFIG_USB_EHCI_MX6 > +#define CONFIG_USB_STORAGE > +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 > +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */ > +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) > +#define CONFIG_MXC_USB_FLAGS 0 > + > +#define ARISTAINETOS2_USB_OTG_PWR IMX_GPIO_NR(4, 15) > +#define ARISTAINETOS2_USB_H1_PWR IMX_GPIO_NR(1, 0) > + > +/* UBI support */ > +#define CONFIG_CMD_MTDPARTS > +#define CONFIG_MTD_PARTITIONS > +#define CONFIG_MTD_DEVICE > +#define CONFIG_RBTREE > +#define CONFIG_LZO > +#define CONFIG_CMD_UBI > +#define CONFIG_CMD_UBIFS > + > +#define CONFIG_MTD_UBI_FASTMAP > +#define CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT 1 > + > +#define CONFIG_HW_WATCHDOG > +#define CONFIG_IMX_WATCHDOG > + > +#define CONFIG_FIT > + > +/* Framebuffer */ > +#define CONFIG_VIDEO > +#define CONFIG_VIDEO_IPUV3 > +/* check this console not needed, after test remove it */ > +#define CONFIG_CFB_CONSOLE > +#define CONFIG_VGA_AS_SINGLE_DEVICE > +#define CONFIG_SYS_CONSOLE_IS_IN_ENV > +#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE > +#define CONFIG_VIDEO_BMP_RLE8 > +#define CONFIG_SPLASH_SCREEN > +#define CONFIG_SPLASH_SCREEN_ALIGN > +#define CONFIG_BMP_16BPP > +#define CONFIG_VIDEO_LOGO > +#define CONFIG_VIDEO_BMP_LOGO > +#define CONFIG_IPUV3_CLK 198000000 > +#define CONFIG_IMX_VIDEO_SKIP > +#define CONFIG_SYS_LDB_CLOCK 33246000 > +#define CONFIG_LG4573 > + > +#define CONFIG_CMD_BMP > + > +#define CONFIG_PWM_IMX > +#define CONFIG_IMX6_PWM_PER_CLK 66000000 > + > +#endif /* __ARISTAINETOS2_CONFIG_H */ > Best regards, Stefano Babic -- ===================================================================== DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de ===================================================================== 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