When SDRAM ECC is enabled and CONFIG_ECC_INIT_VIA_DDRCONTROLLER is not
defined use DMA to set SDRAM to a known state. Previously a sequence of
64-bit stores was used.
Signed-off-by: Peter Tyser <pty...@xes-inc.com>
---
cpu/mpc83xx/spd_sdram.c | 57 +++------------------------------------------
drivers/dma/fsl_dma.c | 16 +++++++++----
include/asm-ppc/config.h | 7 ++---
3 files changed, 18 insertions(+), 62 deletions(-)
diff --git a/cpu/mpc83xx/spd_sdram.c b/cpu/mpc83xx/spd_sdram.c
index 0f61180..8a09a7d 100644
--- a/cpu/mpc83xx/spd_sdram.c
+++ b/cpu/mpc83xx/spd_sdram.c
@@ -825,67 +825,18 @@ long int spd_sdram()
#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
/*
- * Use timebase counter, get_timer() is not availabe
- * at this point of initialization yet.
- */
-static __inline__ unsigned long get_tbms (void)
-{
- unsigned long tbl;
- unsigned long tbu1, tbu2;
- unsigned long ms;
- unsigned long long tmp;
-
- ulong tbclk = get_tbclk();
-
- /* get the timebase ticks */
- do {
- asm volatile ("mftbu %0":"=r" (tbu1):);
- asm volatile ("mftb %0":"=r" (tbl):);
- asm volatile ("mftbu %0":"=r" (tbu2):);
- } while (tbu1 != tbu2);
-
- /* convert ticks to ms */
- tmp = (unsigned long long)(tbu1);
- tmp = (tmp << 32);
- tmp += (unsigned long long)(tbl);
- ms = tmp/(tbclk/1000);
-
- return ms;
-}
-
-/*
* Initialize all of memory for ECC, then enable errors.
*/
void ddr_enable_ecc(unsigned int dram_size)
{
volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
volatile ddr83xx_t *ddr= &immap->ddr;
- unsigned long t_start, t_end;
- register u64 *p;
- register uint size;
- unsigned int pattern[2];
-
- icache_enable();
- t_start = get_tbms();
- pattern[0] = 0xdeadbeef;
- pattern[1] = 0xdeadbeef;
-
-#if defined(CONFIG_DDR_ECC_INIT_VIA_DMA)
- dma_meminit(pattern[0], dram_size);
-#else
- debug("ddr init: CPU FP write method\n");
- size = dram_size;
- for (p = 0; p < (u64*)(size); p++) {
- ppcDWstore((u32*)p, pattern);
- }
- __asm__ __volatile__ ("sync");
-#endif
- t_end = get_tbms();
- icache_disable();
+ debug("\nInitializing ECC!\n");
+
+ dma_meminit(0xdeadbeef, dram_size);
- debug("\nREADY!!\n");
- debug("ddr init duration: %ld ms\n", t_end - t_start);
+ debug("\nREADY!\n");
/* Clear All ECC Errors */
if ((ddr->err_detect & ECC_ERROR_DETECT_MME) == ECC_ERROR_DETECT_MME)
diff --git a/drivers/dma/fsl_dma.c b/drivers/dma/fsl_dma.c
index df33e7a..90a96dd 100644
--- a/drivers/dma/fsl_dma.c
+++ b/drivers/dma/fsl_dma.c
@@ -140,17 +140,19 @@ int dmacpy(phys_addr_t dest, phys_addr_t src, phys_size_t
count) {
}
/*
- * 85xx/86xx use dma to initialize SDRAM when
!CONFIG_ECC_INIT_VIA_DDRCONTROLLER
- * while 83xx uses dma to initialize SDRAM when CONFIG_DDR_ECC_INIT_VIA_DMA
+ * Use dma to initialize SDRAM when !CONFIG_ECC_INIT_VIA_DDRCONTROLLER
*/
-#if ((!defined CONFIG_MPC83xx && defined(CONFIG_DDR_ECC) && \
- !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)) || \
- (defined(CONFIG_MPC83xx) && defined(CONFIG_DDR_ECC_INIT_VIA_DMA)))
+#if (defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER))
void dma_meminit(uint val, uint size)
{
uint *p = 0;
uint i = 0;
+#ifdef CONFIG_MPC83xx
+ /* Enabling the instruction cache greatly improves SDRAM init speed */
+ icache_enable();
+#endif
+
for (*p = 0; p < (uint *)(8 * 1024); p++) {
if (((uint)p & 0x1f) == 0)
ppcDcbz((ulong)p);
@@ -174,5 +176,9 @@ void dma_meminit(uint val, uint size)
for (i = 1; i < size / 0x800000; i++)
dmacpy((0x800000 * i), 0, 0x800000);
+
+#ifdef CONFIG_MPC83xx
+ icache_disable();
+#endif
}
#endif
diff --git a/include/asm-ppc/config.h b/include/asm-ppc/config.h
index ca143c7..01668a9 100644
--- a/include/asm-ppc/config.h
+++ b/include/asm-ppc/config.h
@@ -29,10 +29,9 @@
#endif
#endif
-#ifndef CONFIG_FSL_DMA
-#if ((!defined CONFIG_MPC83xx && defined(CONFIG_DDR_ECC) && \
- !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)) || \
- (defined(CONFIG_MPC83xx) && defined(CONFIG_DDR_ECC_INIT_VIA_DMA)))
+#if (defined(CONFIG_MPC83xx) || defined(CONFIG_MPC85xx) || \
+ defined(CONFIG_MPC86xx)) && !defined CONFIG_FSL_DMA
+#if (defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER))
#define CONFIG_FSL_DMA
#endif
#endif
--
1.6.2.1
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