Hi.
2015-04-29 21:05 GMT+09:00 Jagannadha Sutradharudu Teki
<jagannadh.t...@gmail.com>:
> Replace (1 << nr) to BIT(nr) where nr = 0, 1, 2 .... 31
I assume this patch was generated by a simple sed script or something.
I am opposed to do this globally by script.
See below.
> diff --git a/arch/arm/mach-uniphier/include/mach/ddrphy-regs.h
> b/arch/arm/mach-uniphier/include/mach/ddrphy-regs.h
> index 6b7d600..12ad3e0 100644
> --- a/arch/arm/mach-uniphier/include/mach/ddrphy-regs.h
> +++ b/arch/arm/mach-uniphier/include/mach/ddrphy-regs.h
> @@ -84,16 +84,16 @@ struct ddrphy {
> #define PIR_DRAMRST (1 << 7) /* DRAM Reset */
> #define PIR_DRAMINIT (1 << 8) /* DRAM Initialization */
> #define PIR_WL (1 << 9) /* Write Leveling */
> -#define PIR_QSGATE (1 << 10) /* Read DQS Gate Training */
> -#define PIR_WLADJ (1 << 11) /* Write Leveling Adjust */
> -#define PIR_RDDSKW (1 << 12) /* Read Data Bit Deskew */
> -#define PIR_WRDSKW (1 << 13) /* Write Data Bit Deskew */
> -#define PIR_RDEYE (1 << 14) /* Read Data Eye Training */
> -#define PIR_WREYE (1 << 15) /* Write Data Eye Training */
> -#define PIR_LOCKBYP (1 << 28) /* PLL Lock Bypass */
> -#define PIR_DCALBYP (1 << 29) /* DDL Calibration Bypass */
> -#define PIR_ZCALBYP (1 << 30) /* Impedance Calib Bypass */
> -#define PIR_INITBYP (1 << 31) /* Initialization Bypass */
> +#define PIR_QSGATE BIT(10) /* Read DQS Gate Training */
> +#define PIR_WLADJ BIT(11) /* Write Leveling Adjust */
> +#define PIR_RDDSKW BIT(12) /* Read Data Bit Deskew */
> +#define PIR_WRDSKW BIT(13) /* Write Data Bit Deskew */
> +#define PIR_RDEYE BIT(14) /* Read Data Eye Training */
> +#define PIR_WREYE BIT(15) /* Write Data Eye Training */
> +#define PIR_LOCKBYP BIT(28) /* PLL Lock Bypass */
> +#define PIR_DCALBYP BIT(29) /* DDL Calibration Bypass */
> +#define PIR_ZCALBYP BIT(30) /* Impedance Calib Bypass */
> +#define PIR_INITBYP BIT(31) /* Initialization Bypass */
>
> #define PGSR0_IDONE (1 << 0) /* Initialization Done */
> #define PGSR0_PLDONE (1 << 1) /* PLL Lock Done */
(1 << 7), (1 << 8), (1 << 9) are left unconverted.
OK, you can convert them by adjusting your script, but
I am afraid the indentation is already broken too, i.e. the training
comments are no longer lined up.
>
> #define DXCCR_DQSRES_OPEN (0 << 5)
> -#define DXCCR_DQSRES_688_OHM (1 << 5)
> +#define DXCCR_DQSRES_688_OHM BIT(5)
> #define DXCCR_DQSRES_611_OHM (2 << 5)
> #define DXCCR_DQSRES_550_OHM (3 << 5)
> #define DXCCR_DQSRES_500_OHM (4 << 5)
How about this?
With only (1 << 5) converted, this part looks very strange.
When people look at this, they won't understand what happened.
> diff --git a/drivers/usb/host/xhci.h b/drivers/usb/host/xhci.h
> index 2afa386..886acbc 100644
> --- a/drivers/usb/host/xhci.h
> +++ b/drivers/usb/host/xhci.h
> @@ -44,18 +44,18 @@
> * connect status and port speed are also sticky - meaning they're in
> * the AUX well and they aren't changed by a hot, warm, or cold reset.
> */
> -#define XHCI_PORT_RO ((1 << 0) | (1 << 3) | (0xf << 10) | (1 << 30))
> +#define XHCI_PORT_RO (BIT(0) | BIT(3) | (0xf << 10) | BIT(30))
> /*
> * These bits are RW; writing a 0 clears the bit, writing a 1 sets the bit:
> * bits 5:8, 9, 14:15, 25:27
> * link state, port power, port indicator state, "wake on" enable state
> */
> -#define XHCI_PORT_RWS ((0xf << 5) | (1 << 9) | (0x3 << 14) | (0x7 << 25))
> +#define XHCI_PORT_RWS ((0xf << 5) | BIT(9) | (0x3 << 14) | (0x7 << 25))
I do not want to see stuff like this.
I think you just need to add BIT(nr) macro to include/linux/bitops.h,
and leave the replacement to the maintainer of each file.
If you also do the conversion, please do so with more care.
--
Best Regards
Masahiro Yamada
_______________________________________________
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
