+Albert, +Marek, On Tue, 2015-04-28 at 14:21 +0200, Tomeu Vizoso wrote: > This could happen if we are being chainloaded by Coreboot with LPAE > enabled, as is the case on the Tegra-based Chromebooks. > > Signed-off-by: Tomeu Vizoso <tomeu.viz...@collabora.com>
>From the documentation of recent ARM cores it looks like 0 is the reset value for that register, so explicitly ensuring it has that value seems sane. I'm wary of giving a reviewed-by though as i don't know that part of u-boot well enough to say it's the right spot. However, as we're now using successfully using a Nyan big board with this u-boot patch in kernelci[0] i can happily say: Tested-By: Sjoerd Simons <sjoerd.sim...@collabora.co.uk> 0: http://kernelci.org/boot/tegra124-nyan-big/ > --- > arch/arm/lib/cache-cp15.c | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c > index 0291afa..78fb429 100644 > --- a/arch/arm/lib/cache-cp15.c > +++ b/arch/arm/lib/cache-cp15.c > @@ -96,6 +96,10 @@ static inline void mmu_setup(void) > dram_bank_mmu_setup(i); > } > > + /* Make sure EAE is not enabled */ > + asm volatile("mcr p15, 0, %0, c2, c0, 2" > + : : "r" (0) : "memory"); > + > /* Copy the page table address to cp15 */ > asm volatile("mcr p15, 0, %0, c2, c0, 0" > : : "r" (gd->arch.tlb_addr) : "memory"); _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
