On 02/13/2015 10:57 AM, Curt Brune wrote: > According to the MPC8555/MPC8541 reference manual the SS_EN (source > synchronous enable) bit in the DDR_SDRAM_CLK_CNLT register must be set > during initialization. > > From section 9.4.1.8 of that manual: > > Source synchronous enable. This bit field must be set during > initialization. See Section 9.6.1, "DDR SDRAM Initialization > Sequence," details. > > 0 - Reserved > 1 - The address and command are sent to the DDR SDRAMs source > synchronously. > > In addition, Freescale application note AN2805 is also very clear that > this bit must be set. > > This patch reverts a change introduced by commit > 457caecdbca3df21a93abff19eab12dbc61b7897. > > Testing Done: > > Compiled targets CONFIG_TARGET_MPC8555CDS and CONFIG_TARGET_MPC8541CDS > and inspected the generated assembly code to verify the SS_EN bit was being > set. There is one extra instruction emitted: > > fff9b774: 65 29 80 00 oris r9,r9,32768 > > Compiled the CONFIG_TARGET_MPC8548CDS target and verified that no > additional instructions were emitted related to this patch. > > Booted an image on a MPC8541 based board successfully. > > Signed-off-by: Curt Brune <c...@cumulusnetworks.com> > ---
Applied to mpc85xx master, awaiting upstream. York _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
