On Tue, 2015-03-31 at 13:25 +0300, Alexey Brodkin wrote: > ARCv2 cores may have built-in SLC (System Level Cache, AKA L2-cache). > This change adds functions required for controlling SLC: > * slc_enable/disable > * slc_flush/invalidate > > For now we just disable SLC to escape DMA coherency issues until either: > * SLC flush/invalidate is supported in DMA APIin U-Boot > * hardware DMA coherency is implemented (that might be board specific > so probably we'll need to have a separate Kconfig option for > controlling SLC explicitly) > > Signed-off-by: Alexey Brodkin <abrod...@synopsys.com>
Applied, thanks. -Alexey _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
