From: Thierry Reding <tred...@nvidia.com>
Implement early malloc() support in a similar way as on 32-bit ARM. This
is required for 64-bit Tegra SoCs that initialize from the device tree
just like the earlier 32-bit SoCs.
Cc: Albert Aribaud <albert.u.b...@aribaud.net>
Cc: Marc Zyngier <marc.zyng...@arm.com>
Signed-off-by: Thierry Reding <tred...@nvidia.com>
---
arch/arm/include/asm/config.h | 4 ----
arch/arm/lib/crt0_64.S | 16 ++++++++++++++--
2 files changed, 14 insertions(+), 6 deletions(-)
diff --git a/arch/arm/include/asm/config.h b/arch/arm/include/asm/config.h
index be80434dee4d..7a34a0186cb1 100644
--- a/arch/arm/include/asm/config.h
+++ b/arch/arm/include/asm/config.h
@@ -7,10 +7,6 @@
#ifndef _ASM_CONFIG_H_
#define _ASM_CONFIG_H_
-#ifdef __aarch64__
-#define CONFIG_SYS_GENERIC_GLOBAL_DATA
-#endif
-
#define CONFIG_LMB
#define CONFIG_SYS_BOOT_RAMDISK_HIGH
diff --git a/arch/arm/lib/crt0_64.S b/arch/arm/lib/crt0_64.S
index 77563967e517..010efdbf8f3f 100644
--- a/arch/arm/lib/crt0_64.S
+++ b/arch/arm/lib/crt0_64.S
@@ -62,9 +62,21 @@ ENTRY(_main)
* Set up initial C runtime environment and call board_init_f(0).
*/
ldr x0, =(CONFIG_SYS_INIT_SP_ADDR)
+ mov x1, x0
sub x0, x0, #GD_SIZE /* allocate one GD above SP */
- bic sp, x0, #0xf /* 16-byte alignment for ABI compliance */
- mov x18, sp /* GD is above SP */
+ bic x0, x0, #0xf /* 16-byte alignment for ABI compliance
*/
+ mov x18, x0 /* GD is above SP */
+ mov sp, x0
+clr_gd:
+ str xzr, [x0], #8
+ cmp x0, x1
+ b.lo clr_gd
+#if defined(CONFIG_SYS_MALLOC_F_LEN)
+ ldr x0, =CONFIG_SYS_MALLOC_F_LEN
+ sub x0, sp, x0
+ str x0, [x18, #GD_MALLOC_BASE]
+#endif
+3:
mov x0, #0
bl board_init_f
--
2.3.2
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