[U-Boot] [PATCH v2] T2080QDS/PCIe: Soft Reset PCIe for down-training issue

[Zhao Qiang]

T2080QDS PEX1/Slot#1 will down-train from x4 to x2,
Soft reset PCIe can fix this issue, this is a workaround.

Signed-off-by: Zhao Qiang <b45...@freescale.com>
---
changes for v2
        - modify the commit message

 drivers/pci/fsl_pci_init.c | 17 +++++++++++++++++
 include/configs/T208xQDS.h |  1 +
 2 files changed, 18 insertions(+)

diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c
index 231b075..327fa7d 100644
--- a/drivers/pci/fsl_pci_init.c
+++ b/drivers/pci/fsl_pci_init.c
@@ -481,6 +481,23 @@ void fsl_pci_init(struct pci_controller *hose, struct 
fsl_pci_info *pci_info)
 #endif
        }
 
+#ifdef CONFIG_FSL_PCIE_T2080QDS_RESET
+               int i;
+               /* assert PCIe reset */
+               setbits_be32(&pci->pdb_stat, 0x08000000);
+               (void) in_be32(&pci->pdb_stat);
+               udelay(1000);
+               /* clear PCIe reset */
+               clrbits_be32(&pci->pdb_stat, 0x08000000);
+               asm("sync;isync");
+               for (i = 0; i < 100 && ltssm < PCI_LTSSM_L0; i++) {
+                       pci_hose_read_config_word(hose, dev, PCI_LTSSM,
+                                                 &ltssm);
+                       udelay(1000);
+               }
+
+#endif
+
 #ifdef CONFIG_SYS_P4080_ERRATUM_PCIE_A003
                if (enabled == 0) {
                        serdes_corenet_t *srds_regs = (void 
*)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h
index 395472b..851b4f9 100644
--- a/include/configs/T208xQDS.h
+++ b/include/configs/T208xQDS.h
@@ -558,6 +558,7 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_PCIE2           /* PCIE controler 2 */
 #define CONFIG_PCIE3           /* PCIE controler 3 */
 #define CONFIG_PCIE4           /* PCIE controler 4 */
+#define CONFIG_FSL_PCIE_T2080QDS_RESET
 #define CONFIG_FSL_PCI_INIT    /* Use common FSL init code */
 #define CONFIG_SYS_PCI_64BIT   /* enable 64-bit PCI resources */
 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
-- 
2.1.0.27.g96db324

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