On Thu 2015-02-26 10:45:22, Axel Lin wrote: > By specification the FIFO size would be in a range 2-256 bytes. From TX Level > prospective it means we can set threshold in the range 0-(FIFO size - 1) > bytes. > Hence there are currently two issues: > a) FIFO size 2 bytes is actually skipped since TX Level is 1 bit and could > be > either 0 or 1 byte; > b) FIFO size is incorrectly decreased by 1 which already done by meaning of > TX Level register. > > Fixes: 501943696ea4 (spi: designware_spi: Fix detecting FIFO depth) > Signed-off-by: Andy Shevchenko <andriy.shevche...@linux.intel.com> > Signed-off-by: Axel Lin <axel....@ingics.com>
Acked-by: Pavel Machek <pa...@denx.de> > --- > This fix is from linux-spi tree: > http://git.kernel.org/cgit/linux/kernel/git/broonie/spi.git/commit/?h=for-linus&id=9d239d353c319f9ff884c287ce47feb7cdf60ddc > > drivers/spi/designware_spi.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/spi/designware_spi.c b/drivers/spi/designware_spi.c > index 2624844..8f5c0fc 100644 > --- a/drivers/spi/designware_spi.c > +++ b/drivers/spi/designware_spi.c > @@ -164,13 +164,13 @@ static void spi_hw_init(struct dw_spi_priv *priv) > if (!priv->fifo_len) { > u32 fifo; > > - for (fifo = 2; fifo <= 256; fifo++) { > + for (fifo = 1; fifo < 256; fifo++) { > dw_writew(priv, DW_SPI_TXFLTR, fifo); > if (fifo != dw_readw(priv, DW_SPI_TXFLTR)) > break; > } > > - priv->fifo_len = (fifo == 2) ? 0 : fifo - 1; > + priv->fifo_len = (fifo == 1) ? 0 : fifo; > dw_writew(priv, DW_SPI_TXFLTR, 0); > } > debug("%s: fifo_len=%d\n", __func__, priv->fifo_len); -- (english) http://www.livejournal.com/~pavelmachek (cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
