Hi Gabriel, On Thu, Feb 26, 2015 at 12:27 AM, Gabriel Huau <cont...@huau-gabriel.fr> wrote: > Hi Bin, > > > On 02/24/2015 11:52 PM, Bin Meng wrote: >> >> Hi Gabriel, >> >> On Mon, Feb 16, 2015 at 5:55 AM, Gabriel Huau <cont...@huau-gabriel.fr> >> wrote: >>> >>> Configure the pinctrl as it required to make some IO controllers >>> working (USB/UART/I2C/...). >>> The idea would be in the next version to modify the pch GPIO driver and >>> configure these pins through the device tree. >>> >>> These modifications are ported from the coreboot project. >>> >>> Signed-off-by: Gabriel Huau <cont...@huau-gabriel.fr> >>> --- >>> arch/x86/cpu/baytrail/Makefile | 1 + >>> arch/x86/cpu/baytrail/gpio.c | 206 +++++++++++++++ >>> arch/x86/include/asm/arch-baytrail/gpio.h | 364 >>> ++++++++++++++++++++++++++ >>> arch/x86/include/asm/arch-baytrail/iomap.h | 73 ++++++ >>> arch/x86/include/asm/arch-baytrail/irq.h | 119 +++++++++ >>> arch/x86/include/asm/arch-baytrail/irqroute.h | 67 +++++ >>> arch/x86/include/asm/arch-baytrail/pci_devs.h | 144 ++++++++++ >>> arch/x86/include/asm/arch-baytrail/pmc.h | 253 ++++++++++++++++++ >>> board/intel/minnowmax/minnowmax.c | 212 +++++++++++++++ >>> include/configs/minnowmax.h | 11 + >>> 10 files changed, 1450 insertions(+) >>> create mode 100644 arch/x86/cpu/baytrail/gpio.c >>> create mode 100644 arch/x86/include/asm/arch-baytrail/iomap.h >>> create mode 100644 arch/x86/include/asm/arch-baytrail/irq.h >>> create mode 100644 arch/x86/include/asm/arch-baytrail/irqroute.h >>> create mode 100644 arch/x86/include/asm/arch-baytrail/pci_devs.h >>> create mode 100644 arch/x86/include/asm/arch-baytrail/pmc.h >>> >> [snip] >> >>> diff --git a/include/configs/minnowmax.h b/include/configs/minnowmax.h >>> index 823e051..738c6fa 100644 >>> --- a/include/configs/minnowmax.h >>> +++ b/include/configs/minnowmax.h >>> @@ -69,4 +69,15 @@ >>> /* Avoid a warning in the Realtek Ethernet driver */ >>> #define CONFIG_SYS_CACHELINE_SIZE 16 >>> >>> +/* >>> + * Baytrail has 3 GPIOs bank over PCI, there is no >>> + * driver at the moment so let's disable the command >>> + * and the default x86 driver to avoid any collision >>> + * with the GPIO mapping code. >>> + * @TODO: adding a baytrail-gpio driver and configure >>> + * the muxing through the device tree >>> + */ >>> +#undef CONFIG_INTEL_ICH6_GPIO >>> +#undef CONFIG_CMD_GPIO >>> + >> >> Why undef these two? The BayTrail SoC does support GPIO banks in the >> legacy bridge. > > I might misunderstood the GPIO subsystem but I thought there was 2 banks > available through the PCU iLB GPIO controller which contains the SCORE and > SSUS (102 / 44 pins). > The intel_ich6_gpio has a limitation of 32 GPIOs per bank and I thought it > was just a different controller from the Baytrail, but if I can use it to > control all the GPIOs + doing the IO mapping, I'll be glad to do it!
I checked the BayTrail datasheet. Its GPIO is in the iLB (legacy bridge), which is the same as other IA chipset (Ivybridge, TunnelCreek, Quark). It has 4 banks in core domain and 2 banks in sus domain. So 6 banks in total. You need define 6 gpio nodes in the minnowmax board dts file. You should be able to use the existing gpio driver to configure. >> >>> #endif /* __CONFIG_H */ >>> -- Regards, Bin _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
