Support running U-Boot as a coreboot payload. Tested peripherals include:
- Video (HDMI and DisplayPort)
- SATA disk
- Gigabit Ethernet
- SPI flash
USB3 does not work. This may be a problem with the USB3 PCI driver or
something in the USB3 stack and has not been investigated So far this is
disabled. The SD card slot also does not work.
For video, coreboot will need to run the OPROM to set this up.
With this board, bare support (running without coreboot) is not available
as yet.
Signed-off-by: Simon Glass <s...@chromium.org>
---
arch/x86/Kconfig | 16 +++++++++
arch/x86/dts/Makefile | 1 +
arch/x86/dts/chromebox_panther.dts | 64 ++++++++++++++++++++++++++++++++++
board/google/chromebox_panther/Kconfig | 18 ++++++++++
configs/chromebox_panther_defconfig | 11 ++++++
include/configs/chromebox_panther.h | 17 +++++++++
6 files changed, 127 insertions(+)
create mode 100644 arch/x86/dts/chromebox_panther.dts
create mode 100644 board/google/chromebox_panther/Kconfig
create mode 100644 configs/chromebox_panther_defconfig
create mode 100644 include/configs/chromebox_panther.h
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index fef11f3..6c667ae 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -32,6 +32,20 @@ config TARGET_CHROMEBOOK_LINK
and it provides a 2560x1700 high resolution touch-enabled LCD
display.
+config TARGET_CHROMEBOX_PANTHER
+ bool "Support Chromebox panther (not available)"
+ select n
+ help
+ Note: At present this must be used with Coreboot. See README.x86
+ for instructions.
+
+ This is the Asus Chromebox CN60 released in 2014. It uses an Intel
+ Haswell Celeron 2955U Dual Core CPU with 2GB of SDRAM. It has a
+ Lynx Point platform controller hub, PCIe WiFi and Bluetooth. It also
+ includes a USB SD reader, four USB3 ports, display port and HDMI
+ video output and a 16GB SATA solid state drive. There is no Chrome
+ OS EC on this model.
+
config TARGET_CROWNBAY
bool "Support Intel Crown Bay CRB"
help
@@ -420,6 +434,8 @@ source "board/coreboot/coreboot/Kconfig"
source "board/google/chromebook_link/Kconfig"
+source "board/google/chromebox_panther/Kconfig"
+
source "board/intel/crownbay/Kconfig"
source "board/intel/minnowmax/Kconfig"
diff --git a/arch/x86/dts/Makefile b/arch/x86/dts/Makefile
index 7a66133..431bbd8 100644
--- a/arch/x86/dts/Makefile
+++ b/arch/x86/dts/Makefile
@@ -1,4 +1,5 @@
dtb-y += chromebook_link.dtb \
+ chromebox_panther.dtb \
crownbay.dtb \
galileo.dtb \
minnowmax.dtb
diff --git a/arch/x86/dts/chromebox_panther.dts
b/arch/x86/dts/chromebox_panther.dts
new file mode 100644
index 0000000..01d43e4
--- /dev/null
+++ b/arch/x86/dts/chromebox_panther.dts
@@ -0,0 +1,64 @@
+/dts-v1/;
+
+/include/ "skeleton.dtsi"
+/include/ "serial.dtsi"
+
+/ {
+ model = "Google Panther";
+ compatible = "google,panther", "intel,celeron-haswell";
+
+ aliases {
+ spi0 = "/spi";
+ };
+
+ config {
+ silent-console = <0>;
+ no-keyboard;
+ };
+
+ gpioa {
+ compatible = "intel,ich6-gpio";
+ u-boot,dm-pre-reloc;
+ reg = <0 0x10>;
+ bank-name = "A";
+ };
+
+ gpiob {
+ compatible = "intel,ich6-gpio";
+ u-boot,dm-pre-reloc;
+ reg = <0x30 0x10>;
+ bank-name = "B";
+ };
+
+ gpioc {
+ compatible = "intel,ich6-gpio";
+ u-boot,dm-pre-reloc;
+ reg = <0x40 0x10>;
+ bank-name = "C";
+ };
+
+ chosen {
+ stdout-path = "/serial";
+ };
+
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "intel,ich-spi";
+ spi-flash@0 {
+ #size-cells = <1>;
+ #address-cells = <1>;
+ reg = <0>;
+ compatible = "winbond,w25q64", "spi-flash";
+ memory-map = <0xff800000 0x00800000>;
+ rw-mrc-cache {
+ label = "rw-mrc-cache";
+ /* Alignment: 4k (for updating) */
+ reg = <0x003e0000 0x00010000>;
+ type = "wiped";
+ wipe-value = [ff];
+ };
+ };
+ };
+
+};
diff --git a/board/google/chromebox_panther/Kconfig
b/board/google/chromebox_panther/Kconfig
new file mode 100644
index 0000000..788b122
--- /dev/null
+++ b/board/google/chromebox_panther/Kconfig
@@ -0,0 +1,18 @@
+if TARGET_CHROMEBOX_PANTHER
+
+config SYS_BOARD
+ default "chromebox_panther"
+
+config SYS_VENDOR
+ default "google"
+
+config SYS_SOC
+ default "haswell"
+
+config SYS_CONFIG_NAME
+ default "chromebox_panther"
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+
+endif
diff --git a/configs/chromebox_panther_defconfig
b/configs/chromebox_panther_defconfig
new file mode 100644
index 0000000..cbde39e
--- /dev/null
+++ b/configs/chromebox_panther_defconfig
@@ -0,0 +1,11 @@
+CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xfff00000"
+CONFIG_X86=y
+CONFIG_TARGET_CHROMEBOX_PANTHER=y
+CONFIG_OF_CONTROL=y
+CONFIG_OF_SEPARATE=y
+CONFIG_DEFAULT_DEVICE_TREE="chromebox_panther"
+CONFIG_HAVE_MRC=y
+CONFIG_SMM_TSEG_SIZE=0x800000
+CONFIG_VIDEO_VESA=y
+CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
+CONFIG_FRAMEBUFFER_VESA_MODE_11A=y
diff --git a/include/configs/chromebox_panther.h
b/include/configs/chromebox_panther.h
new file mode 100644
index 0000000..00fe26d
--- /dev/null
+++ b/include/configs/chromebox_panther.h
@@ -0,0 +1,17 @@
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <configs/x86-common.h>
+#include <configs/x86-chromebook.h>
+
+#define CONFIG_RTL8169
+/* Avoid a warning in the Realtek Ethernet driver */
+#define CONFIG_SYS_CACHELINE_SIZE 16
+
+#endif /* __CONFIG_H */
--
2.2.0.rc0.207.ga3a616c
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