On 02/05/2015 03:10 PM, Jörg Krause wrote:
On Do, 2015-02-05 at 08:33 -0700, Stephen Warren wrote:
On 02/05/2015 04:21 AM, Jörg Krause wrote:
...
This reminded me about an issue I had some months ago:
http://lists.denx.de/pipermail/u-boot/2014-July/182885.html
I enabled debug output in arch/arm/cpu/arm926ejs/cache.c and I get
error:
=> tftp u-boot.sb
using ci_udc, OUT ep- IN ep- STATUS ep-
CACHE: Misaligned operation at range [43f7b010, 43f7b070]
I removed the flush_cache() call in cmd_net.c:netboot_common() as
suggested by Marek in the thread. But the error message is still there.
Perhaps make flush_cache() a macro that also passes in the file/line
number where it's called from, and print those out along with he
"misaligned operation" error message?
(or find some other way to perform a stack dump from within that function).
I've added in each function in ci_udc a printf statement before a cache
function is called, eg:
static void ci_flush_qh(int ep_num)
{
[..]
printf("CACHE: flush_dcache_range %s %d
\n",__FUNCTION__,__LINE__);
flush_dcache_range(start, end);
}
I've also looked at all calling functions of flush_cache or
flush_dcache_range, but I think there is nothing of relevance.
This is a snippet of the output:
...
CACHE: flush_dcache_range ci_bounce 356
CACHE: Misaligned operation at range [43f7b010, 43f7b070]
timeout sending packets to usb ethernet
ping failed; host 10.0.0.1 is not alive
Which git commit did you build, and which board?
I'm curious what values you have for ARCH_DMA_MINALIGN and
CONFIG_SYS_CACHELINE_SIZE.
Are you sure flush_dcache_range() is the code printing the alignment
error, not e.g. invalidate_dcache_range()?
The reason I ask most of these questions is that line 356 mentioned in
your debug spew is in function ci_debounce() in the code I have; no
doubt I have a different git commit than you have checked out, and the
debug printfs you added changed the line numbers too.
About the only thing I can think of is that:
a) You're not using an up-to-date ci_udc.c; IIRC I fixed quite a few
cache issues when I reworked it a while back.
b) In ci_bounce(), the bounce buffer is only allocated if the
user-buffer is already aligned, and if a large-enough bounce buffer
wasn't previously allocated. If ci_req->b_buf was uninitialized it could
be non-zero (thus preventing the expected aligned allocation) yet not
actually aligned enough.
c) Perhaps ARCH_DMA_MINALIGN or CONFIG_SYS_CACHELINE_SIZE aren't correct
or are inconsistent.
Ah. I note that check_cache_range() in either arch/arm/cpu/arm1136/cpu.c
or arch/arm/cpu/arm926ejs/cache.c uses CONFIG_SYS_CACHELINE_SIZE to
check for alignment, whereas ci_udc.c uses ARCH_DMA_MINALIGN.
Inconsistency between those two could be at fault.
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