Allow r0 to be used for other purposes in this file.

Signed-off-by: Simon Glass <s...@chromium.org>
---

 arch/arm/cpu/armv7/start.S | 88 +++++++++++++++++++++++-----------------------
 1 file changed, 44 insertions(+), 44 deletions(-)

diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S
index 70048c1..c5f94ef 100644
--- a/arch/arm/cpu/armv7/start.S
+++ b/arch/arm/cpu/armv7/start.S
@@ -38,13 +38,13 @@ reset:
         * disable interrupts (FIQ and IRQ), also set the cpu to SVC32 mode,
         * except if in HYP mode already
         */
-       mrs     r0, cpsr
-       and     r1, r0, #0x1f           @ mask mode bits
+       mrs     r2, cpsr
+       and     r1, r2, #0x1f           @ mask mode bits
        teq     r1, #0x1a               @ test for HYP mode
-       bicne   r0, r0, #0x1f           @ clear all mode bits
-       orrne   r0, r0, #0x13           @ set SVC mode
-       orr     r0, r0, #0xc0           @ disable FIQ and IRQ
-       msr     cpsr,r0
+       bicne   r2, r2, #0x1f           @ clear all mode bits
+       orrne   r2, r2, #0x13           @ set SVC mode
+       orr     r2, r2, #0xc0           @ disable FIQ and IRQ
+       msr     cpsr, r2
 
 /*
  * Setup vector:
@@ -53,13 +53,13 @@ reset:
  */
 #if !(defined(CONFIG_OMAP44XX) && defined(CONFIG_SPL_BUILD))
        /* Set V=0 in CP15 SCTLR register - for VBAR to point to vector */
-       mrc     p15, 0, r0, c1, c0, 0   @ Read CP15 SCTLR Register
-       bic     r0, #CR_V               @ V = 0
-       mcr     p15, 0, r0, c1, c0, 0   @ Write CP15 SCTLR Register
+       mrc     p15, 0, r2, c1, c0, 0   @ Read CP15 SCTLR Register
+       bic     r2, #CR_V               @ V = 0
+       mcr     p15, 0, r2, c1, c0, 0   @ Write CP15 SCTLR Register
 
        /* Set vector address in CP15 VBAR register */
-       ldr     r0, =_start
-       mcr     p15, 0, r0, c12, c0, 0  @Set VBAR
+       ldr     r2, =_start
+       mcr     p15, 0, r2, c12, c0, 0  @Set VBAR
 #endif
 
        /* the mask ROM code should have PLL and others stable */
@@ -77,9 +77,9 @@ ENTRY(c_runtime_cpu_setup)
  * If I-cache is enabled invalidate it
  */
 #ifndef CONFIG_SYS_ICACHE_OFF
-       mcr     p15, 0, r0, c7, c5, 0   @ invalidate icache
-       mcr     p15, 0, r0, c7, c10, 4  @ DSB
-       mcr     p15, 0, r0, c7, c5, 4   @ ISB
+       mcr     p15, 0, r2, c7, c5, 0   @ invalidate icache
+       mcr     p15, 0, r2, c7, c10, 4  @ DSB
+       mcr     p15, 0, r2, c7, c5, 4   @ ISB
 #endif
 
        bx      lr
@@ -88,7 +88,7 @@ ENDPROC(c_runtime_cpu_setup)
 
 /*************************************************************************
  *
- * void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3)
+ * void save_boot_params(u32 r2, u32 r1, u32 r2, u32 r3)
  *     __attribute__((weak));
  *
  * Stack pointer is not yet initialized at this moment
@@ -112,55 +112,55 @@ ENTRY(cpu_init_cp15)
        /*
         * Invalidate L1 I/D
         */
-       mov     r0, #0                  @ set up for MCR
-       mcr     p15, 0, r0, c8, c7, 0   @ invalidate TLBs
-       mcr     p15, 0, r0, c7, c5, 0   @ invalidate icache
-       mcr     p15, 0, r0, c7, c5, 6   @ invalidate BP array
-       mcr     p15, 0, r0, c7, c10, 4  @ DSB
-       mcr     p15, 0, r0, c7, c5, 4   @ ISB
+       mov     r2, #0                  @ set up for MCR
+       mcr     p15, 0, r2, c8, c7, 0   @ invalidate TLBs
+       mcr     p15, 0, r2, c7, c5, 0   @ invalidate icache
+       mcr     p15, 0, r2, c7, c5, 6   @ invalidate BP array
+       mcr     p15, 0, r2, c7, c10, 4  @ DSB
+       mcr     p15, 0, r2, c7, c5, 4   @ ISB
 
        /*
         * disable MMU stuff and caches
         */
-       mrc     p15, 0, r0, c1, c0, 0
-       bic     r0, r0, #0x00002000     @ clear bits 13 (--V-)
-       bic     r0, r0, #0x00000007     @ clear bits 2:0 (-CAM)
-       orr     r0, r0, #0x00000002     @ set bit 1 (--A-) Align
-       orr     r0, r0, #0x00000800     @ set bit 11 (Z---) BTB
+       mrc     p15, 0, r2, c1, c0, 0
+       bic     r2, r2, #0x00002000     @ clear bits 13 (--V-)
+       bic     r2, r2, #0x00000007     @ clear bits 2:0 (-CAM)
+       orr     r2, r2, #0x00000002     @ set bit 1 (--A-) Align
+       orr     r2, r2, #0x00000800     @ set bit 11 (Z---) BTB
 #ifdef CONFIG_SYS_ICACHE_OFF
-       bic     r0, r0, #0x00001000     @ clear bit 12 (I) I-cache
+       bic     r2, r2, #0x00001000     @ clear bit 12 (I) I-cache
 #else
-       orr     r0, r0, #0x00001000     @ set bit 12 (I) I-cache
+       orr     r2, r2, #0x00001000     @ set bit 12 (I) I-cache
 #endif
-       mcr     p15, 0, r0, c1, c0, 0
+       mcr     p15, 0, r2, c1, c0, 0
 
 #ifdef CONFIG_ARM_ERRATA_716044
-       mrc     p15, 0, r0, c1, c0, 0   @ read system control register
-       orr     r0, r0, #1 << 11        @ set bit #11
-       mcr     p15, 0, r0, c1, c0, 0   @ write system control register
+       mrc     p15, 0, r2, c1, c0, 0   @ read system control register
+       orr     r2, r2, #1 << 11        @ set bit #11
+       mcr     p15, 0, r2, c1, c0, 0   @ write system control register
 #endif
 
 #if (defined(CONFIG_ARM_ERRATA_742230) || defined(CONFIG_ARM_ERRATA_794072))
-       mrc     p15, 0, r0, c15, c0, 1  @ read diagnostic register
-       orr     r0, r0, #1 << 4         @ set bit #4
-       mcr     p15, 0, r0, c15, c0, 1  @ write diagnostic register
+       mrc     p15, 0, r2, c15, c0, 1  @ read diagnostic register
+       orr     r2, r2, #1 << 4         @ set bit #4
+       mcr     p15, 0, r2, c15, c0, 1  @ write diagnostic register
 #endif
 
 #ifdef CONFIG_ARM_ERRATA_743622
-       mrc     p15, 0, r0, c15, c0, 1  @ read diagnostic register
-       orr     r0, r0, #1 << 6         @ set bit #6
-       mcr     p15, 0, r0, c15, c0, 1  @ write diagnostic register
+       mrc     p15, 0, r2, c15, c0, 1  @ read diagnostic register
+       orr     r2, r2, #1 << 6         @ set bit #6
+       mcr     p15, 0, r2, c15, c0, 1  @ write diagnostic register
 #endif
 
 #ifdef CONFIG_ARM_ERRATA_751472
-       mrc     p15, 0, r0, c15, c0, 1  @ read diagnostic register
-       orr     r0, r0, #1 << 11        @ set bit #11
-       mcr     p15, 0, r0, c15, c0, 1  @ write diagnostic register
+       mrc     p15, 0, r2, c15, c0, 1  @ read diagnostic register
+       orr     r2, r2, #1 << 11        @ set bit #11
+       mcr     p15, 0, r2, c15, c0, 1  @ write diagnostic register
 #endif
 #ifdef CONFIG_ARM_ERRATA_761320
-       mrc     p15, 0, r0, c15, c0, 1  @ read diagnostic register
-       orr     r0, r0, #1 << 21        @ set bit #21
-       mcr     p15, 0, r0, c15, c0, 1  @ write diagnostic register
+       mrc     p15, 0, r2, c15, c0, 1  @ read diagnostic register
+       orr     r2, r2, #1 << 21        @ set bit #21
+       mcr     p15, 0, r2, c15, c0, 1  @ write diagnostic register
 #endif
 
        mov     pc, lr                  @ back to my caller
-- 
2.2.0.rc0.207.ga3a616c

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