On 21:35 Tue 23 Jun , Po-Yu Chuang wrote:
> This patch adds support for A320 development board from Faraday. This board
> uses FA526 processor by default and has 512kB and 32MB NOR flash, 64M RAM.
> FA526 is an ARMv4 processor and uses the ARM920T source in this patch.
>
> Signed-off-by: Po-Yu Chuang <ratb...@faraday-tech.com>
> ---
please use git
please add a MAKEALL and MAINTAINER entry
> Index: Makefile
> ===================================================================
> RCS file: /usr/local/cvsroot/ctd/u-boot-2009.06/Makefile,v
> retrieving revision 1.1.1.1
> diff -u -r1.1.1.1 Makefile
> --- Makefile 15 Jun 2009 06:47:34 -0000 1.1.1.1
> +++ Makefile 23 Jun 2009 06:45:36 -0000
> @@ -2940,6 +2940,13 @@
> @$(MKCONFIG) $(@:_config=) arm s3c44b0 B2 dave
>
> #########################################################################
> +## Faraday A320 Systems
> +#########################################################################
> +
> +a320_config : unconfig
> + @$(MKCONFIG) $(@:_config=) arm arm920t a320 faraday
920T but you write 926ejs in the config.mk?
> +
> +#########################################################################
> ## ARM720T Systems
> #########################################################################
>
<snip>
> Index: board/faraday/a320/board.c
> ===================================================================
> RCS file: board/faraday/a320/board.c
> diff -N board/faraday/a320/board.c
> --- /dev/null 1 Jan 1970 00:00:00 -0000
> +++ board/faraday/a320/board.c 23 Jun 2009 06:06:34 -0000 1.3
> @@ -0,0 +1,120 @@
> +/*
> + * (C) Copyright 2009 Faraday Technology
> + * Po-Yu Chuang <ratb...@faraday-tech.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
> + */
> +
> +#include <common.h>
> +#include <netdev.h>
> +#include <rtc.h>
> +
> +#include "ftsmc.h"
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +#define FLASH_BANK0_CONFIG (FTSMC_BANK_ENABLE | \
> + FTSMC_BANK_BASE(PHYS_FLASH_1) | \
> + FTSMC_BANK_SIZE_1M | \
> + FTSMC_BANK_MBW_8)
> +
> +#define FLASH_BANK0_TIMING (FTSMC_TPR_RBE | \
> + FTSMC_TPR_AST(3) | \
> + FTSMC_TPR_CTW(3) | \
> + FTSMC_TPR_ATI(0xf) | \
> + FTSMC_TPR_AT2(3) | \
> + FTSMC_TPR_WTC(3) | \
> + FTSMC_TPR_AHT(3) | \
> + FTSMC_TPR_TRNA(0xf))
> +
> +#define FLASH_BANK1_CONFIG (FTSMC_BANK_ENABLE | \
> + FTSMC_BANK_BASE(PHYS_FLASH_2) | \
> + FTSMC_BANK_SIZE_32M | \
> + FTSMC_BANK_MBW_32 )
> +
> +#define FLASH_BANK1_TIMING (FTSMC_TPR_AST(3) | \
> + FTSMC_TPR_CTW(3) | \
> + FTSMC_TPR_ATI(0xf) | \
> + FTSMC_TPR_AT2(3) | \
> + FTSMC_TPR_WTC(3) | \
> + FTSMC_TPR_AHT(3) | \
> + FTSMC_TPR_TRNA(0xf))
please move this to config header
> +
> +extern int timer_init (void);
no-need please remove
> +
> +/*
> + * Miscellaneous platform dependent initialisations
> + */
> +
> +static void
> +ftsmc_setup_bank (int bank, unsigned int config, unsigned int timing)
is this board or soc specific?
> +{
> + volatile struct ftsmc *smc = (struct ftsmc *)CONFIG_SYS_SMC_BASE;
> +
> + if (bank < 0 || bank > 3) {
> + printf ("bank # %d invalid\n", bank);
> + return;
> + }
> +
> + smc->bank[bank].cr = cpu_to_le32 (config);
> + smc->bank[bank].tpr = cpu_to_le32 (timing);
please use proper accessor everywhere
> +}
> +
> +/* initialize Flash */
> +static void ftsmc_init (void)
> +{
> + ftsmc_setup_bank (0, FLASH_BANK0_CONFIG, FLASH_BANK0_TIMING);
> + ftsmc_setup_bank (1, FLASH_BANK1_CONFIG, FLASH_BANK1_TIMING);
> +}
> +
> +int board_init (void)
> +{
> + gd->bd->bi_arch_number = MACH_TYPE_FARADAY;
> +
> + ftsmc_init ();
> + rtc_reset ();
do you really need this so early the rtc and enable everytime?
> + timer_init ();
no-need pelase remove
> + return 0;
> +}
> +
> +int dram_init (void)
> +{
> + gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
> + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
> +
> + return 0;
> +}
> +
> +int board_eth_init (bd_t * bd)
> +{
> + return ftmac100_initialize (bd);
> +}
> +
> +ulong board_flash_get_legacy (ulong base, int banknum, flash_info_t * info)
> +{
> + if (banknum == 0) { /* non-CFI boot flash */
> + info->portwidth = FLASH_CFI_8BIT;
> + info->chipwidth = FLASH_CFI_BY8;
> + info->interface = FLASH_CFI_X8;
> + return 1;
> + } else
> + return 0;
> +}
> +
> +int interrupt_init (void)
> +{
> + /* nothing happens here - we don't setup any IRQs */
> + return (0);
> +}
no-need please remove
> Index: board/faraday/a320/config.mk
> ===================================================================
> RCS file: board/faraday/a320/config.mk
> diff -N board/faraday/a320/config.mk
> --- /dev/null 1 Jan 1970 00:00:00 -0000
> +++ board/faraday/a320/config.mk 16 Jun 2009 13:45:54 -0000 1.1
> @@ -0,0 +1,35 @@
> +#
> +# (C) Copyright 2009 Faraday Technology
> +# Po-Yu Chuang <ratb...@faraday-tech.com>
> +#
> +# This program is free software; you can redistribute it and/or
> +# modify it under the terms of the GNU General Public License as
> +# published by the Free Software Foundation; either version 2 of
> +# the License, or (at your option) any later version.
> +#
> +# This program is distributed in the hope that it will be useful,
> +# but WITHOUT ANY WARRANTY; without even the implied warranty of
> +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> +# GNU General Public License for more details.
> +#
> +# You should have received a copy of the GNU General Public License
> +# along with this program; if not, write to the Free Software
> +# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> +# MA 02111-1307 USA
> +#
> +
> +# Faraday A320 board with FA526/FA626TE/ARM926EJ-S cpus
??
> +#
> +# see http://www.faraday-tech.com/ for more information
> +
> +# A320 has 1 bank of 64 MB DRAM (after remapped)
> +#
> +# 0000'0000 to 0400'0000
> +#
> +# Linux-Kernel is expected to be at 0000'8000, entry 0000'8000
> +#
> +# we load ourself to 03f8'0000
> +#
> +# download area is 0200'0000
> +
> +TEXT_BASE = 0x03f80000
<snip>
> Index: board/faraday/a320/ftahbc.h
> Index: board/faraday/a320/ftpmu.h
> Index: board/faraday/a320/ftsdmc.h
> Index: board/faraday/a320/ftsmc.h
> Index: board/faraday/a320/fttmr.h
If I undersand correctly all those header are soc specific not board specific
as the timer code
so please move the header to
include/asm-arm/arch-faraday or your soc familiy name
and the code to
cpu/armxxx/faraday/
> Index: board/faraday/a320/lowlevel_init.S
> ===================================================================
> RCS file: board/faraday/a320/lowlevel_init.S
> diff -N board/faraday/a320/lowlevel_init.S
> --- /dev/null 1 Jan 1970 00:00:00 -0000
> +++ board/faraday/a320/lowlevel_init.S 23 Jun 2009 06:45:15 -0000
> 1.3
> @@ -0,0 +1,205 @@
> +/*
> + * (C) Copyright 2009 Faraday Technology
> + * Po-Yu Chuang <ratb...@faraday-tech.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
> + */
> +
> +#include <config.h>
> +#include <version.h>
> +#include "ftahbc.h"
> +#include "ftsdmc.h"
> +
> +/*
> + * Memory Mapping
> + */
> +#define CONFIG_SYS_ROM_DEFAULT 0x00000000
> +#define CONFIG_SYS_SDRAM_DEFAULT 0x10000000
> +#define CONFIG_SYS_SDRAM_REMAPPED PHYS_SDRAM_1 /* remap location */
I guess this board specific too
> +
> +/*
> + * numeric 7 segment display
> + */
> +.macro led, num, rtmp1, rtmp2
> + mov \rtmp1, #\num
> + ldr \rtmp2, =CONFIG_SYS_DEBUG_LED
> + str \rtmp1, [\rtmp2]
> +.endm
please use write32
> +
> +.global reset_cpu
> +reset_cpu:
> + b reset_cpu
> +
> +.globl lowlevel_init
> +lowlevel_init:
> + mov r11, lr
> +
> + led 0x0, r0, r1
> +
> + /* if REMAP bit is set -> memory had been initialzed */
> +
> + ldr r0, =CONFIG_SYS_AHBC_BASE
> + ldr r1, [r0, #FTAHBC_OFFSET_ICR]
> + tst r1, #FTAHBC_ICR_REMAP @ test REMAP bit
> + bne 1f
> +
> + bl init_sdmc
> +
> + led 0x1, r0, r1
> +
> + /*
> + * copy U-Boot to RAM
> + */
> +copy_code:
> + ldr r0, =CONFIG_SYS_ROM_DEFAULT /* r0 <- source address */
> + ldr r1, =CONFIG_SYS_SDRAM_DEFAULT /* r1 <- target address */
> +
> + ldr r2, .LC5
> + ldr r3, .LC6
> + sub r2, r3, r2 /* r2 <- size of armboot */
> + add r2, r0, r2 /* r2 <- source end address */
> +
> +copy_loop:
> + ldmia r0!, {r3-r10} /* copy from source address [r0] */
> + stmia r1!, {r3-r10} /* copy to target address [r1] */
> + cmp r0, r2 /* until source end addreee [r2] */
> + ble copy_loop
why???
it's already done in the start.S
> +
> + led 0x2, r0, r1
> +
> + bl remap
> +1:
> + led 0x3, r0, r1
> +
> + /* everything is fine now */
> + mov lr, r11
> + mov pc, lr
> +
> +.LC5:
> + .word _start
> +.LC6:
> + .word __bss_start
> +
> +/*
> + * memory initialization
> + */
> +init_sdmc:
> + mov r9, lr
> +
please use write32 and co when it's possible
include/asm-arm/macro.h
> + /* set SDRAM register */
> + ldr r0, =CONFIG_SYS_SDMC_BASE
> + ldr r1, tp0
> + str r1, [r0, #FTSDMC_OFFSET_TP0]
> + ldr r1, tp1
> + str r1, [r0, #FTSDMC_OFFSET_TP1]
> +
> + /* set to precharge */
> + mov r1, #FTSDMC_CR_IPREC
> + str r1, [r0, #FTSDMC_OFFSET_CR]
> +
> + /* Waiting for SDRAM to set up */
> +4:
> + ldr r1, [r0, #FTSDMC_OFFSET_CR]
> + cmp r1, #0
> + bne 4b
> +
> + /* set mode register */
> + ldr r1, =FTSDMC_CR_ISMR
> + str r1, [r0, #FTSDMC_OFFSET_CR]
> +
> + /* Waiting for SDRAM to set up */
> +5:
> + ldr r1, [r0, #FTSDMC_OFFSET_CR]
> + cmp r1, #0
> + bne 5b
> +
> + /* set to refresh */
> + mov r1, #FTSDMC_CR_IREF
> + str r1, [r0, #FTSDMC_OFFSET_CR]
> +
> + /* Waiting for SDRAM to set up */
> +6:
> + ldr r1, [r0, #FTSDMC_OFFSET_CR]
> + cmp r1, #0
> + bne 6b
> +
> + ldr r1, b0_bsr
> + ldr r2, =FTSDMC_BANK_BASE(CONFIG_SYS_SDRAM_DEFAULT)
> + orr r1, r1, r2
> + str r1, [r0, #FTSDMC_OFFSET_BANK0_BSR] @ bank 0
> +
> + ldr r1, =0x0
> + str r1, [r0, #FTSDMC_OFFSET_BANK1_BSR] @ bank 1 (clear/disable)
> + str r1, [r0, #FTSDMC_OFFSET_BANK2_BSR] @ bank 2 (clear/disable)
> + str r1, [r0, #FTSDMC_OFFSET_BANK3_BSR] @ bank 3 (clear/disable)
> + str r1, [r0, #FTSDMC_OFFSET_BANK4_BSR] @ bank 4 (clear/disable)
> + str r1, [r0, #FTSDMC_OFFSET_BANK5_BSR] @ bank 5 (clear/disable)
> + str r1, [r0, #FTSDMC_OFFSET_BANK6_BSR] @ bank 6 (clear/disable)
> + str r1, [r0, #FTSDMC_OFFSET_BANK7_BSR] @ bank 7 (clear/disable)
> +
> + ldr r1, =FTSDMC_ACR_TOC(0x18)
> + str r1, [r0, #FTSDMC_OFFSET_ACR] @ arbiter
> +
> + mov lr, r9
> + mov pc, lr
> +
> +/*
> + * This code will remap the memory ROM and SDRAM
> + * ROM will be placed on 0x80000000 SDRAM will jump to 0x0
> + */
> +remap:
> + mov r9, lr
> +
> + ldr r0, =CONFIG_SYS_SDMC_BASE
> +
> + /* first adjust sdram */
> + ldr r1, b0_bsr
> + ldr r2, =FTSDMC_BANK_BASE(CONFIG_SYS_SDRAM_REMAPPED)
> + orr r1, r1, r2
> + str r1, [r0, #FTSDMC_OFFSET_BANK0_BSR] @ bank 0
> +
> + /* then remap */
> + ldr r3, =CONFIG_SYS_AHBC_BASE
> + ldr r4, [r3, #FTAHBC_OFFSET_ICR]
> + orr r4, r4, #FTAHBC_ICR_REMAP @ Set REMAP bit
> + str r4, [r3, #FTAHBC_OFFSET_ICR]
> +
> + mov lr, r9
> + mov pc, lr
> +
> +/*
> + * some parameters for the board
> + */
> +tp0: .word FTSDMC_TP0_TRAS(2) | \
> + FTSDMC_TP0_TRP(1) | \
> + FTSDMC_TP0_TRCD(1) | \
> + FTSDMC_TP0_TRF(3) | \
> + FTSDMC_TP0_TWR(1) | \
> + FTSDMC_TP0_TCL(2)
> +
> +tp1: .word FTSDMC_TP1_INI_PREC(4) | \
> + FTSDMC_TP1_INI_REFT(8) | \
> + FTSDMC_TP1_REF_INTV(0x180)
> +
> +b0_bsr: .word FTSDMC_BANK_ENABLE | \
> + FTSDMC_BANK_DDW_X16 | \
> + FTSDMC_BANK_DSZ_256M | \
> + FTSDMC_BANK_MBW_32 | \
> + FTSDMC_BANK_SIZE_64M
those config will need to the config head
> Index: board/faraday/a320/u-boot.lds
no need please remove
> Index: include/configs/a320.h
> ===================================================================
> RCS file: include/configs/a320.h
> diff -N include/configs/a320.h
> --- /dev/null 1 Jan 1970 00:00:00 -0000
> +++ include/configs/a320.h 23 Jun 2009 06:25:54 -0000 1.3
> @@ -0,0 +1,181 @@
> +/*
> + * (C) Copyright 2009 Faraday Technology
> + * Po-Yu Chuang <ratb...@faraday-tech.com>
> + *
> + * Configuation settings for the Faraday A320 board.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
> + */
> +
> +#ifndef __CONFIG_H
> +#define __CONFIG_H
> +
> +/*-----------------------------------------------------------------------
> + * CPU and Board Configuration Options
> + */
> +#define CONFIG_A320 /* in a Faraday A320 SoC/Board */
> +
> +#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
> +
> +#undef CONFIG_SKIP_LOWLEVEL_INIT
> +
> +/*-----------------------------------------------------------------------
> + * Timer
> + */
> +#define CONFIG_SYS_HZ 32768 /* timer ticks per second */
1000 mandatory
> +#define CONFIG_SYS_TIMERBASE 0x98400000
is it board specific??
> +
> +/*-----------------------------------------------------------------------
> + * RTC
> + */
> +#define CONFIG_RTC_FTRTC
> +#define CONFIG_SYS_RTC_BASE 0x98600000
ditto
> +
> +/*-----------------------------------------------------------------------
> + * Serial console configuration
> + */
> +
> +/* FTUART is a high speed NS 16C550A compatible UART */
> +#define CONFIG_BAUDRATE 38400
> +#define CONFIG_CONS_INDEX 1
> +#define CONFIG_SYS_NS16550
> +#define CONFIG_SYS_NS16550_SERIAL
> +#define CONFIG_SYS_NS16550_COM1 0x98200000
> +#define CONFIG_SYS_NS16550_REG_SIZE -4
> +#define CONFIG_SYS_NS16550_CLK 18432000
> +
> +/* valid baudrates */
> +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
> +
> +/*-----------------------------------------------------------------------
> + * Ethernet
> + */
> +#define CONFIG_NET_MULTI
> +#define CONFIG_DRIVER_FTMAC100
> +#define CONFIG_SYS_MAC100_BASE 0x90900000
ditto
> +
> +#define CONFIG_BOOTDELAY 3
> +#define CONFIG_ETHADDR c3:10:da:ce:3f:3e
> +#define CONFIG_NETMASK 255.255.255.0
> +#define CONFIG_IPADDR 192.168.68.55
> +#define CONFIG_SERVERIP 192.168.68.63
please remove the mac and ip config
> +
> +/*-----------------------------------------------------------------------
> + * Hardware register bases
> + */
> +#define CONFIG_SYS_AHBC_BASE 0x90100000 /* AHB Controller */
> +#define CONFIG_SYS_SMC_BASE 0x90200000 /* Static Memory Controller */
> +#define CONFIG_SYS_DEBUG_LED 0x902ffffc /* Debug LED */
> +#define CONFIG_SYS_SDMC_BASE 0x90300000 /* SDRAM Controller */
is it board specific??
> +
> +#define CONFIG_SYS_FTPMU_BASE 0x98100000 /* Power Management
> Unit */
is it board specific??
> +
> +/*-----------------------------------------------------------------------
> + * Command line configuration.
> + */
> +#include <config_cmd_default.h>
> +
> +#define CONFIG_CMD_CACHE
> +#define CONFIG_CMD_DATE
> +#define CONFIG_CMD_PING
> +
> +/*-----------------------------------------------------------------------
> + * Miscellaneous configurable options
> + */
> +#define CONFIG_SYS_LONGHELP /* undef to save memory */
> +#define CONFIG_SYS_PROMPT "A320 # " /* Monitor Command Prompt */
> +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
> +
> +/* Print Buffer Size */
> +#define CONFIG_SYS_PBSIZE \
> + (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
> +
> +/* max number of command args */
> +#define CONFIG_SYS_MAXARGS 16
> +
> +/* Boot Argument Buffer Size */
> +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
> +
> +/*-----------------------------------------------------------------------
> + * Stack sizes
> + *
> + * The stack sizes are set up in start.S using the settings below
> + */
> +#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
> +#ifdef CONFIG_USE_IRQ
> +#define CONFIG_STACKSIZE_IRQ (4 * 1024) /* IRQ stack */
> +#define CONFIG_STACKSIZE_FIQ (4 * 1024) /* FIQ stack */
> +#endif
> +
> +/*-----------------------------------------------------------------------
> + * Size of malloc() pool
> + */
> +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024)
> +
> +/*-----------------------------------------------------------------------
> + * size in bytes reserved for initial data
> +*/
> +#define CONFIG_SYS_GBL_DATA_SIZE 128
> +
> +/*-----------------------------------------------------------------------
> + * Physical Memory Map
> + */
> +#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
> +#define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */
> +#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
> +
> +/*
> + * Load address and memory test area should agree with
> + * board/faraday/a320/config.mk. Be careful not to overwrite U-boot itself.
> + */
> +#define CONFIG_SYS_LOAD_ADDR 0x02000000
> +
> +/* memtest works on 63 MB in DRAM */
> +#define CONFIG_SYS_MEMTEST_START 0x00000000
> +#define CONFIG_SYS_MEMTEST_END 0x03F00000
> +
> +/*-----------------------------------------------------------------------
> + * FLASH and environment organization
> + */
> +
> +/* no environments */
> +#define CONFIG_ENV_IS_NOWHERE
you do not plan to store the env in nor?
> +
> +/* Total Size of Environment Sector */
> +#define CONFIG_ENV_SIZE 0x20000
> +
Best Regards,
J.
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