MATRIX VISION GmbH, Talstraße 16, DE-71570 Oppenweiler Registergericht: Amtsgericht Stuttgart, HRB 271090 Geschäftsführer: Gerhard Thullner, Werner Armingeon, Uwe Furtner, Hans-Joachim Reich
rebased with minor fixes of invalid factory defaults. use common code. Signed-off-by: Andre Schwarz <andre.schw...@matrix-vision.de> --- board/matrix_vision/mvblm7/mvblm7.c | 54 +++++++++++++++------------------- board/matrix_vision/mvblm7/mvblm7.h | 3 +- board/matrix_vision/mvblm7/pci.c | 32 ++------------------ include/configs/MVBLM7.h | 52 ++++++++++++++++----------------- 4 files changed, 54 insertions(+), 87 deletions(-) diff --git a/board/matrix_vision/mvblm7/mvblm7.c b/board/matrix_vision/mvblm7/mvblm7.c index 6984af9..53d873a 100644 --- a/board/matrix_vision/mvblm7/mvblm7.c +++ b/board/matrix_vision/mvblm7/mvblm7.c @@ -42,8 +42,15 @@ int fixed_sdram(void) u32 msize = 0; u32 ddr_size; u32 ddr_size_log2; + char *s = getenv("ddr_size"); msize = CONFIG_SYS_DDR_SIZE; + if (s) { + u32 env_ddr_size = simple_strtoul(s, NULL, 10); + if (env_ddr_size == 512) + msize = 512; + } + for (ddr_size = msize << 20, ddr_size_log2 = 0; (ddr_size > 1); ddr_size = ddr_size >> 1, ddr_size_log2++) { @@ -63,14 +70,19 @@ int fixed_sdram(void) im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG; im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2; im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE; + im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2; im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL; - im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL; + im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL; - udelay(300); + asm("sync;isync"); + udelay(600); im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; - return CONFIG_SYS_DDR_SIZE; + asm("sync;isync"); + udelay(500); + + return msize; } phys_size_t initdram(int board_type) @@ -88,40 +100,22 @@ phys_size_t initdram(int board_type) return msize * 1024 * 1024; } -int checkboard(void) +int misc_init_r(void) { - puts("Board: Matrix Vision mvBlueLYNX-M7\n"); - - return 0; -} + char *s = getenv("reset_env"); -u8 *dhcp_vendorex_prep(u8 *e) -{ - char *ptr; - - /* DHCP vendor-class-identifier = 60 */ - ptr = getenv("dhcp_vendor-class-identifier"); - if (ptr) { - *e++ = 60; - *e++ = strlen(ptr); - while (*ptr) - *e++ = *ptr++; - } - /* DHCP_CLIENT_IDENTIFIER = 61 */ - ptr = getenv("dhcp_client_id"); - if (ptr) { - *e++ = 61; - *e++ = strlen(ptr); - while (*ptr) - *e++ = *ptr++; + if (s) { + mv_reset_environment(); } - return e; + return 0; } -u8 *dhcp_vendorex_proc(u8 *popt) +int checkboard(void) { - return NULL; + puts("Board: Matrix Vision mvBlueLYNX-M7\n"); + + return 0; } #ifdef CONFIG_HARD_SPI diff --git a/board/matrix_vision/mvblm7/mvblm7.h b/board/matrix_vision/mvblm7/mvblm7.h index 03e9f41..de9fec7 100644 --- a/board/matrix_vision/mvblm7/mvblm7.h +++ b/board/matrix_vision/mvblm7/mvblm7.h @@ -8,14 +8,13 @@ #define FPGA_DIN 0x20000000 #define FPGA_STATUS 0x10000000 #define FPGA_CONF_DONE 0x08000000 -#define MMC_CS 0x04000000 #define WD_WDI 0x00400000 #define WD_TS 0x00200000 #define MAN_RST 0x00100000 #define MV_GPIO_DAT (WD_TS) -#define MV_GPIO_OUT (FPGA_CONFIG|FPGA_DIN|FPGA_CCLK|WD_TS|WD_WDI|MMC_CS) +#define MV_GPIO_OUT (FPGA_CONFIG|FPGA_DIN|FPGA_CCLK|MVBLM7_MMC_CS) #define MV_GPIO_ODE (FPGA_CONFIG|MAN_RST) #endif diff --git a/board/matrix_vision/mvblm7/pci.c b/board/matrix_vision/mvblm7/pci.c index 9f31719..3ed0b80 100644 --- a/board/matrix_vision/mvblm7/pci.c +++ b/board/matrix_vision/mvblm7/pci.c @@ -35,21 +35,6 @@ DECLARE_GLOBAL_DATA_PTR; -int mvblm7_load_fpga(void) -{ - size_t data_size = 0; - void *fpga_data = NULL; - char *datastr = getenv("fpgadata"); - char *sizestr = getenv("fpgadatasize"); - - if (datastr) - fpga_data = (void *)simple_strtoul(datastr, NULL, 16); - if (sizestr) - data_size = (size_t)simple_strtoul(sizestr, NULL, 16); - - return fpga_load(0, fpga_data, data_size); -} - static struct pci_region pci_regions[] = { { bus_start: CONFIG_SYS_PCI1_MEM_BASE, @@ -84,32 +69,23 @@ void pci_init_board(void) volatile law83xx_t *pci_law; struct pci_region *reg[] = { pci_regions }; - load_fpga = 1; immr = (immap_t *) CONFIG_SYS_IMMR; clk = (clk83xx_t *) &immr->clk; pci_ctrl = immr->pci_ctrl; pci_law = immr->sysconf.pcilaw; gpio = (volatile gpio83xx_t *)&immr->gpio[0]; - s = getenv("skip_fpga"); - if (s) { - printf("found 'skip_fpga' -> FPGA _not_ loaded !\n"); - load_fpga = 0; - } - gpio->dat = MV_GPIO_DAT; gpio->odr = MV_GPIO_ODE; - if (load_fpga) - gpio->dir = MV_GPIO_OUT; - else - gpio->dir = MV_GPIO_OUT & ~(FPGA_DIN|FPGA_CCLK); + gpio->dir = MV_GPIO_OUT; printf("SICRH / SICRL : 0x%08x / 0x%08x\n", immr->sysconf.sicrh, immr->sysconf.sicrl); mvblm7_init_fpga(); - if (load_fpga) - mvblm7_load_fpga(); + mv_load_fpga(); + + gpio->dir = MV_GPIO_OUT & ~(FPGA_DIN|FPGA_CCLK); /* Enable PCI_CLK_OUTPUTs 0 and 1 with 1:1 clocking */ clk->occr = 0xc0000000; diff --git a/include/configs/MVBLM7.h b/include/configs/MVBLM7.h index 9675205..02ff0ca 100644 --- a/include/configs/MVBLM7.h +++ b/include/configs/MVBLM7.h @@ -46,13 +46,15 @@ #define CONFIG_TSEC_ENET #define CONFIG_MPC8XXX_SPI #define CONFIG_HARD_SPI -#define MVBLM7_MMC_CS 0x04000000 +#define MVBLM7_MMC_CS 0x04000000 +#define CONFIG_MISC_INIT_R /* I2C */ #undef CONFIG_SOFT_I2C #define CONFIG_FSL_I2C #define CONFIG_I2C_MULTI_BUS +#define CONFIG_I2C_CMD_TREE #define CONFIG_SYS_I2C_OFFSET 0x3000 #define CONFIG_SYS_I2C2_OFFSET 0x3100 @@ -62,44 +64,42 @@ /* * DDR Setup */ +#undef CONFIG_SPD_EEPROM + #define CONFIG_SYS_DDR_BASE 0x00000000 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE #define CONFIG_SYS_83XX_DDR_USES_CS0 1 #define CONFIG_SYS_MEMTEST_START (60<<20) #define CONFIG_SYS_MEMTEST_END (70<<20) +#define CONFIG_VERY_BIG_RAM -#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ - DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 +#define CONFIG_SYS_DDRCDR 0x22000001 +#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 -#define CONFIG_SYS_DDR_SIZE 256 +#define CONFIG_SYS_DDR_SIZE 512 -/* HC, 75Ohm, DDR-II, DRQ */ -#define CONFIG_SYS_DDRCDR 0x80000001 -/* EN, ODT_WR, 3BA, 14row, 10col */ -#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014102 +#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202 #define CONFIG_SYS_DDR_CS1_CONFIG 0x0 #define CONFIG_SYS_DDR_CS2_CONFIG 0x0 #define CONFIG_SYS_DDR_CS3_CONFIG 0x0 -#define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f -#define CONFIG_SYS_DDR_CS1_BNDS 0x0 -#define CONFIG_SYS_DDR_CS2_BNDS 0x0 -#define CONFIG_SYS_DDR_CS3_BNDS 0x0 - -#define CONFIG_SYS_DDR_CLK_CNTL 0x02000000 +#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f +#define CONFIG_SYS_DDR_CS1_BNDS 0x0 +#define CONFIG_SYS_DDR_CS2_BNDS 0x0 +#define CONFIG_SYS_DDR_CS3_BNDS 0x0 -#define CONFIG_SYS_DDR_TIMING_0 0x00260802 -#define CONFIG_SYS_DDR_TIMING_1 0x2625b221 -#define CONFIG_SYS_DDR_TIMING_2 0x1f9820c7 -#define CONFIG_SYS_DDR_TIMING_3 0x00000000 +#define CONFIG_SYS_DDR_TIMING_0 0x00260802 +#define CONFIG_SYS_DDR_TIMING_1 0x3837c322 +#define CONFIG_SYS_DDR_TIMING_2 0x0f9848c6 +#define CONFIG_SYS_DDR_TIMING_3 0x00000000 -/* ~MEM_EN, SREN, DDR-II, 32_BE */ -#define CONFIG_SYS_DDR_SDRAM_CFG 0x43080000 +#define CONFIG_SYS_DDR_SDRAM_CFG 0x43080008 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 -#define CONFIG_SYS_DDR_INTERVAL 0x04060100 +#define CONFIG_SYS_DDR_INTERVAL 0x02000100 -#define CONFIG_SYS_DDR_MODE 0x078e0232 +#define CONFIG_SYS_DDR_MODE 0x04040242 +#define CONFIG_SYS_DDR_MODE2 0x00800000 /* Flash */ #define CONFIG_SYS_FLASH_CFI @@ -193,8 +193,6 @@ #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 #define CONFIG_SYS_PCI1_IO_SIZE 0x01000000 -#define _IO_BASE 0x00000000 - #define CONFIG_NET_MULTI 1 #define CONFIG_NET_RETRY_COUNT 3 @@ -407,8 +405,8 @@ #define MV_CI mvBL-M7 #define MV_VCI mvBL-M7 -#define MV_FPGA_DATA 0xfff80000 -#define MV_FPGA_SIZE 0x00076ca2 +#define MV_FPGA_DATA 0xfff40000 +#define MV_FPGA_SIZE 0 #define MV_KERNEL_ADDR 0xff810000 #define MV_INITRD_ADDR 0xffb00000 #define MV_SOURCE_ADDR 0xff804000 @@ -455,7 +453,7 @@ "static_ipaddr=192.168.90.10\0" \ "static_netmask=255.255.255.0\0" \ "static_gateway=0.0.0.0\0" \ - "initrd_name=uInitrd.mvblm7-xenorfs\0" \ + "initrd_name=uInitrd.mvBL-M7-rfs\0" \ "zcip=no\0" \ "netboot=yes\0" \ "mvtest=Ff\0" \ -- 1.6.0.4
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