From: Dinh Nguyen <dingu...@opensource.altera.com>

This sets the CPU clocks to 925MHz and DDR to 400MHz.

Signed-off-by: Dinh Nguyen <dingu...@opensource.altera.com>
---
 board/altera/socfpga/pll_config.h | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/board/altera/socfpga/pll_config.h 
b/board/altera/socfpga/pll_config.h
index f0f59a9..3992ff7 100644
--- a/board/altera/socfpga/pll_config.h
+++ b/board/altera/socfpga/pll_config.h
@@ -12,13 +12,13 @@
 /* PLL configuration data */
 /* Main PLL */
 #define CONFIG_HPS_MAINPLLGRP_VCO_DENOM                        (0)
-#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER                        (63)
+#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER                        (73)
 #define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT               (0)
 #define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT              (0)
 #define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT             (0)
-#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT          (3)
-#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT     (3)
-#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT       (12)
+#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT          (4)
+#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT     (0)
+#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT       (14)
 #define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK          (1)
 #define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK          (1)
 #define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK          (1)
-- 
2.2.1

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