From: Dinh Nguyen <dingu...@opensource.altera.com>
s_init will map SDRAM to 0x0.
Signed-off-by: Dinh Nguyen <dingu...@opensource.altera.com>
---
arch/arm/cpu/armv7/socfpga/Makefile | 2 +-
arch/arm/cpu/armv7/socfpga/s_init.c | 49 ++++++++++++++++++++++
arch/arm/include/asm/arch-socfpga/system_manager.h | 10 +++++
3 files changed, 60 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/cpu/armv7/socfpga/s_init.c
diff --git a/arch/arm/cpu/armv7/socfpga/Makefile
b/arch/arm/cpu/armv7/socfpga/Makefile
index 9bd649d..c51c292 100644
--- a/arch/arm/cpu/armv7/socfpga/Makefile
+++ b/arch/arm/cpu/armv7/socfpga/Makefile
@@ -8,6 +8,6 @@
#
obj-y := lowlevel_init.o
-obj-y += misc.o timer.o reset_manager.o system_manager.o clock_manager.o \
+obj-y += s_init.o misc.o timer.o reset_manager.o system_manager.o
clock_manager.o \
fpga_manager.o sdram.o
obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o scan_manager.o
diff --git a/arch/arm/cpu/armv7/socfpga/s_init.c
b/arch/arm/cpu/armv7/socfpga/s_init.c
new file mode 100644
index 0000000..d9d29df
--- /dev/null
+++ b/arch/arm/cpu/armv7/socfpga/s_init.c
@@ -0,0 +1,49 @@
+/*
+ * Copyright (C) 2014 Altera Corporation <www.altera.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <spl.h>
+#include <watchdog.h>
+#include <asm/io.h>
+#include <asm/spl.h>
+#include <asm/arch/system_manager.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * First C function to initialize the critical hardware early
+ */
+void s_init(void)
+{
+#ifdef CONFIG_SPL_BUILD
+ struct socfpga_system_manager *sysmgr_regs =
+ (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
+ unsigned long reg;
+ /*
+ * First C code to run. Clear fake OCRAM ECC first as SBE
+ * and DBE might triggered during power on
+ */
+ reg = readl(&sysmgr_regs->eccgrp_ocram);
+ if (reg & SYSMGR_ECC_OCRAM_SERR)
+ writel(SYSMGR_ECC_OCRAM_SERR | SYSMGR_ECC_OCRAM_EN,
+ &sysmgr_regs->eccgrp_ocram);
+ if (reg & SYSMGR_ECC_OCRAM_DERR)
+ writel(SYSMGR_ECC_OCRAM_DERR | SYSMGR_ECC_OCRAM_EN,
+ &sysmgr_regs->eccgrp_ocram);
+#else
+ /*
+ * Private components security
+ * U-Boot : configure private timer, global timer and cpu
+ * component access as non secure for kernel stage (as required
+ * by kernel)
+ */
+ setbits_le32(SOCFPGA_SCU_SNSAC, 0xfff);
+
+#endif /* CONFIG_SPL_BUILD */
+
+ /* Configure the L2 controller to make SDRAM start at 0 */
+ writel(0x1, (SOCFPGA_MPUL2_ADDRESS + SOCFPGA_MPUL2_ADRFLTR_START));
+}
diff --git a/arch/arm/include/asm/arch-socfpga/system_manager.h
b/arch/arm/include/asm/arch-socfpga/system_manager.h
index 51d9815..10659f7 100644
--- a/arch/arm/include/asm/arch-socfpga/system_manager.h
+++ b/arch/arm/include/asm/arch-socfpga/system_manager.h
@@ -144,4 +144,14 @@ struct socfpga_system_manager {
#define SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB 2
#define SYSMGR_EMACGRP_CTRL_PHYSEL_MASK 0x3
+/*
+ * SCU Non-secure Access Control
+ */
+#define SOCFPGA_SCU_SNSAC (SOCFPGA_MPUSCU_ADDRESS + 0x54)
+/*
+ * L2 PL-310
+ * for configuring L2 address filtering start address in assembly.
+ */
+#define SOCFPGA_MPUL2_ADRFLTR_START (0xC00)
+
#endif /* _SYSTEM_MANAGER_H_ */
--
2.2.1
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