Greetings,
Our board have one PHY's SMI attached via GPIO (bitBang SMI)
and the other network device (a switch) connected to the 8360e's real SMI
controller.
This patch aims to make u-boot able to use both at the same time. I am checking
if I am
on the right track and if I have missed something.
The board-specific header file #define looks like this (similar to the
FIXED_PHY) method
[snip]
#define CONFIG_SYS_BITBANG_PHY_PORT(devnum) devnum,
#define CONFIG_SYS_BITBANG_PHY_PORTS \
CONFIG_SYS_BITBANG_PHY_PORT(10)
[/snip]
My code's baseline is at commit 57fe30194d3c15c37d9ff06dbd2a4c1ffccda018 (post
v2009.06)
Thank you for everyone's time.
- Richard
From 644a9cd7b9d9331989a3cf59d920a072c9dafe05 Mon Sep 17 00:00:00 2001
From: Richard Retanubun <richardretanu...@ruggedcom.com>
Date: Wed, 17 Jun 2009 16:00:41 -0400
Subject: [PATCH] 83xx: UEC: Added support for bitBang MII driver access to PHYs
This patch enabled support for having PHYs on bitBang MII and uec MII
operating at the same time.
---
drivers/net/phy/miiphybb.c | 28 ++++++++++++++++++++++------
drivers/net/phy/miiphybb.h | 26 ++++++++++++++++++++++++++
drivers/qe/uec.c | 6 ++----
drivers/qe/uec_phy.c | 34 ++++++++++++++++++++++++++++++++++
4 files changed, 84 insertions(+), 10 deletions(-)
create mode 100644 drivers/net/phy/miiphybb.h
diff --git a/drivers/net/phy/miiphybb.c b/drivers/net/phy/miiphybb.c
index e3c163a..1a15707 100644
--- a/drivers/net/phy/miiphybb.c
+++ b/drivers/net/phy/miiphybb.c
@@ -29,6 +29,7 @@
#include <common.h>
#include <ioports.h>
#include <ppc_asm.tmpl>
+#include "miiphybb.h"
/*****************************************************************************
*
@@ -38,8 +39,13 @@
static void miiphy_pre (char read, unsigned char addr, unsigned char reg)
{
int j; /* counter */
-#if !(defined(CONFIG_EP8248) || defined(CONFIG_EP82XXM))
- volatile ioport_t *iop = ioport_addr ((immap_t *) CONFIG_SYS_IMMR,
MDIO_PORT);
+#if !(defined(CONFIG_EP8248) || defined(CONFIG_EP82XXM)) \
+ && !defined(CONFIG_MPC83XX)
+ volatile gpio_n_t *iop = ioport_addr ((immap_t *) CONFIG_SYS_IMMR,
MDIO_PORT);
+#elif defined(CONFIG_MPC83XX)
+ volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
+ volatile qepio83xx_t *par_io = (volatile qepio83xx_t *)&im->qepio;
+ volatile gpio_n_t *iop = &(par_io->ioport[MDIO_PORT]);
#endif
/*
@@ -123,8 +129,13 @@ int bb_miiphy_read (char *devname, unsigned char addr,
{
short rdreg; /* register working value */
int j; /* counter */
-#if !(defined(CONFIG_EP8248) || defined(CONFIG_EP82XXM))
- volatile ioport_t *iop = ioport_addr ((immap_t *) CONFIG_SYS_IMMR,
MDIO_PORT);
+#if !(defined(CONFIG_EP8248) || defined(CONFIG_EP82XXM)) \
+ && !defined(CONFIG_MPC83XX)
+ volatile gpio_n_t *iop = ioport_addr ((immap_t *) CONFIG_SYS_IMMR,
MDIO_PORT);
+#elif defined(CONFIG_MPC83XX)
+ volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
+ volatile qepio83xx_t *par_io = (volatile qepio83xx_t *)&im->qepio;
+ volatile gpio_n_t *iop = &(par_io->ioport[MDIO_PORT]);
#endif
miiphy_pre (1, addr, reg);
@@ -190,8 +201,13 @@ int bb_miiphy_write (char *devname, unsigned char addr,
unsigned char reg, unsigned short value)
{
int j; /* counter */
-#if !(defined(CONFIG_EP8248) || defined(CONFIG_EP82XXM))
- volatile ioport_t *iop = ioport_addr ((immap_t *) CONFIG_SYS_IMMR,
MDIO_PORT);
+#if !(defined(CONFIG_EP8248) || defined(CONFIG_EP82XXM)) \
+ && !defined(CONFIG_MPC83XX)
+ volatile gpio_n_t *iop = ioport_addr ((immap_t *) CONFIG_SYS_IMMR,
MDIO_PORT);
+#elif defined(CONFIG_MPC83XX)
+ volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
+ volatile qepio83xx_t *par_io = (volatile qepio83xx_t *)&im->qepio;
+ volatile gpio_n_t *iop = &(par_io->ioport[MDIO_PORT]);
#endif
miiphy_pre (0, addr, reg);
diff --git a/drivers/net/phy/miiphybb.h b/drivers/net/phy/miiphybb.h
new file mode 100644
index 0000000..4fff40d
--- /dev/null
+++ b/drivers/net/phy/miiphybb.h
@@ -0,0 +1,26 @@
+/*
+ * Copyright (C) 2006-2009 RuggedCom, Inc.
+ *
+ * Richard Retanubun <richardretanu...@ruggedcom.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+int bb_miiphy_read (char *devname, unsigned char addr,
+ unsigned char reg, unsigned short *value);
+
+int bb_miiphy_write (char *devname, unsigned char addr,
+ unsigned char reg, unsigned short value);
diff --git a/drivers/qe/uec.c b/drivers/qe/uec.c
index 63fede9..a9bac99 100644
--- a/drivers/qe/uec.c
+++ b/drivers/qe/uec.c
@@ -579,8 +579,7 @@ static void phy_change(struct eth_device *dev)
adjust_link(dev);
}
-#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) \
- && !defined(BITBANGMII)
+#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) /*&& !defined(BITBANGMII)*/
/*
* Find a device index from the devlist by name
@@ -1383,8 +1382,7 @@ int uec_initialize(bd_t *bis, uec_info_t *uec_info)
return err;
}
-#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) \
- && !defined(BITBANGMII)
+#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) /* &&
!defined(CONFIG_BITBANGMII) */
miiphy_register(dev->name, uec_miiphy_read, uec_miiphy_write);
#endif
diff --git a/drivers/qe/uec_phy.c b/drivers/qe/uec_phy.c
index d613f3e..c7c7439 100644
--- a/drivers/qe/uec_phy.c
+++ b/drivers/qe/uec_phy.c
@@ -25,6 +25,7 @@
#include "uec.h"
#include "uec_phy.h"
#include "miiphy.h"
+#include "../net/phy/miiphybb.h"
#define ugphy_printk(format, arg...) \
printf(format "\n", ## arg)
@@ -92,6 +93,15 @@ static const struct fixed_phy_port fixed_phy_port[] = {
CONFIG_SYS_FIXED_PHY_PORTS /* defined in board configuration file */
};
+/* BitBang MII support for ethernet ports */
+#ifndef CONFIG_SYS_BITBANG_PHY_PORTS
+#define CONFIG_SYS_BITBANG_PHY_PORTS /* default is an empty array */
+#endif
+
+static const unsigned short bitbang_phy_port[] = {
+ CONFIG_SYS_BITBANG_PHY_PORTS /* defined in board configuration file */
+};
+
static void config_genmii_advert (struct uec_mii_info *mii_info);
static void genmii_setup_forced (struct uec_mii_info *mii_info);
static void genmii_restart_aneg (struct uec_mii_info *mii_info);
@@ -112,6 +122,18 @@ void uec_write_phy_reg (struct eth_device *dev, int
mii_id, int regnum, int valu
enet_tbi_mii_reg_e mii_reg = (enet_tbi_mii_reg_e) regnum;
u32 tmp_reg;
+
+#if defined(CONFIG_BITBANGMII)
+ u8 i = 0;
+
+ for (i = 0; i < ARRAY_SIZE(bitbang_phy_port); i++) {
+ if (mii_id == bitbang_phy_port[i]) {
+ (void)bb_miiphy_write(NULL, mii_id, regnum, value);
+ return;
+ }
+ }
+#endif /* CONFIG_BITBANGMII */
+
ug_regs = ugeth->uec_mii_regs;
/* Stop the MII management read cycle */
@@ -139,6 +161,18 @@ int uec_read_phy_reg (struct eth_device *dev, int mii_id,
int regnum)
u32 tmp_reg;
u16 value;
+
+#if defined(CONFIG_BITBANGMII)
+ u8 i = 0;
+
+ for (i = 0; i < ARRAY_SIZE(bitbang_phy_port); i++) {
+ if (mii_id == bitbang_phy_port[i]) {
+ (void)bb_miiphy_read(NULL, mii_id, regnum, &value);
+ return (value);
+ }
+ }
+#endif /* CONFIG_BITBANGMII */
+
ug_regs = ugeth->uec_mii_regs;
/* Setting up the MII Mangement Address Register */
--
1.6.2.4
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