Hi Emil,
On 07/12/2014 18:59, Emil Renner Berthing wrote:
> Signed-off-by: Emil Renner Berthing <u-b...@esmil.dk>
> ---
> arch/arm/Kconfig | 5 +
> arch/arm/include/asm/arch-mx5/iomux-mx51.h | 19 ++
> arch/arm/include/asm/mach-types.h | 13 +
> board/hercules/mx51_na04/Kconfig | 15 +
> board/hercules/mx51_na04/MAINTAINERS | 6 +
> board/hercules/mx51_na04/Makefile | 10 +
> board/hercules/mx51_na04/mx51_na04.c | 469
> +++++++++++++++++++++++++++++
> configs/mx51_na04_defconfig | 3 +
> include/configs/mx51_na04.h | 246 +++++++++++++++
> 9 files changed, 786 insertions(+)
> create mode 100644 board/hercules/mx51_na04/Kconfig
> create mode 100644 board/hercules/mx51_na04/MAINTAINERS
> create mode 100644 board/hercules/mx51_na04/Makefile
> create mode 100644 board/hercules/mx51_na04/mx51_na04.c
> create mode 100644 configs/mx51_na04_defconfig
> create mode 100644 include/configs/mx51_na04.h
>
Can you split your patch ? It does not only add your board.
Changes in iomux-mx51.h should flow into a separate patch, because they
are not board specific.
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index 0982117..f8c4429 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -581,6 +581,10 @@ config TARGET_MX51_EFIKAMX
> bool "Support mx51_efikamx"
> select CPU_V7
>
> +config TARGET_MX51_NA04
> + bool "Support the Hercules eCAFE Slim/EX HD laptops"
> + select CPU_V7
> +
> config TARGET_VISION2
> bool "Support vision2"
> select CPU_V7
> @@ -911,6 +915,7 @@ source "board/freescale/mx6sxsabresd/Kconfig"
> source "board/freescale/vf610twr/Kconfig"
> source "board/gateworks/gw_ventana/Kconfig"
> source "board/genesi/mx51_efikamx/Kconfig"
> +source "board/hercules/mx51_na04/Kconfig"
> source "board/gumstix/pepper/Kconfig"
> source "board/h2200/Kconfig"
> source "board/hale/tt01/Kconfig"
> diff --git a/arch/arm/include/asm/arch-mx5/iomux-mx51.h
> b/arch/arm/include/asm/arch-mx5/iomux-mx51.h
> index 70aaa37..91dde62 100644
> --- a/arch/arm/include/asm/arch-mx5/iomux-mx51.h
> +++ b/arch/arm/include/asm/arch-mx5/iomux-mx51.h
> @@ -71,6 +71,7 @@ enum {
> MX51_PAD_EIM_A25__USBH2_DIR = IOMUX_PAD(0x454, 0x0c0, 2,
> __NA_, 0, MX51_USBH_PAD_CTRL),
> MX51_PAD_EIM_A26__GPIO2_20 = IOMUX_PAD(0x458, 0x0c4, 1,
> __NA_, 0, MX51_GPIO_PAD_CTRL),
> MX51_PAD_EIM_A26__USBH2_STP = IOMUX_PAD(0x458, 0x0c4, 2,
> __NA_, 0, MX51_USBH_PAD_CTRL),
> + MX51_PAD_EIM_A27__GPIO2_21 = IOMUX_PAD(0x45c, 0x0c8, 1,
> __NA_, 0, MX51_GPIO_PAD_CTRL),
> MX51_PAD_EIM_A27__USBH2_NXT = IOMUX_PAD(0x45c, 0x0c8, 2,
> __NA_, 0, MX51_USBH_PAD_CTRL),
> MX51_PAD_EIM_EB2__FEC_MDIO = IOMUX_PAD(0x468, 0x0d4, 3,
> 0x954, 0, PAD_CTL_PUS_22K_UP | PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH |
> PAD_CTL_HYS),
> MX51_PAD_EIM_EB3__FEC_RDATA1 = IOMUX_PAD(0x46c, 0x0d8, 3,
> 0x95c, 0, NO_PAD_CTRL),
> @@ -105,6 +106,7 @@ enum {
> MX51_PAD_NANDF_CLE__PATA_RESET_B = IOMUX_PAD(0x4f0, 0x114, 1,
> __NA_, 0, NO_PAD_CTRL),
> MX51_PAD_NANDF_WP_B__PATA_DMACK = IOMUX_PAD(0x4f4, 0x118, 1,
> __NA_, 0, NO_PAD_CTRL),
> MX51_PAD_NANDF_RB0__PATA_DMARQ = IOMUX_PAD(0x4f8, 0x11c, 1,
> __NA_, 0, NO_PAD_CTRL),
> + MX51_PAD_NANDF_RB0__SD3_DATA3 = IOMUX_PAD(0x4f8, 0x11c, 2,
> 0x948, 0, MX51_SDHCI_PAD_CTRL),
> MX51_PAD_NANDF_RB1__PATA_IORDY = IOMUX_PAD(0x4fc, 0x120, 1,
> __NA_, 0, NO_PAD_CTRL),
> MX51_PAD_NANDF_RB2__FEC_COL = IOMUX_PAD(0x500, 0x124, 1,
> 0x94c, 0, MX51_PAD_CTRL_2),
> MX51_PAD_NANDF_RB2__GPIO3_10 = IOMUX_PAD(0x500, 0x124, 3,
> __NA_, 0, MX51_GPIO_PAD_CTRL),
> @@ -122,23 +124,32 @@ enum {
> MX51_PAD_NANDF_CS6__FEC_TDATA3 = IOMUX_PAD(0x530, 0x148, 2,
> __NA_, 0, MX51_PAD_CTRL_5),
> MX51_PAD_NANDF_CS6__PATA_DA_2 = IOMUX_PAD(0x530, 0x148, 1,
> __NA_, 0, NO_PAD_CTRL),
> MX51_PAD_NANDF_CS7__FEC_TX_EN = IOMUX_PAD(0x534, 0x14c, 1,
> __NA_, 0, MX51_PAD_CTRL_5),
> + MX51_PAD_NANDF_CS7__SD3_CLK = IOMUX_PAD(0x534, 0x14c, 5,
> __NA_, 0, MX51_SDHCI_PAD_CTRL),
> MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK = IOMUX_PAD(0x538, 0x150, 1,
> 0x974, 0, MX51_PAD_CTRL_4),
> + MX51_PAD_NANDF_RDY_INT__SD3_CMD = IOMUX_PAD(0x538, 0x150, 0x15,
> __NA_, 0, MX51_SDHCI_PAD_CTRL),
> MX51_PAD_NANDF_D15__GPIO3_25 = IOMUX_PAD(0x53c, 0x154, 3,
> __NA_, 0, MX51_GPIO_PAD_CTRL),
> MX51_PAD_NANDF_D15__PATA_DATA15 = IOMUX_PAD(0x53c, 0x154, 1,
> __NA_, 0, NO_PAD_CTRL),
> + MX51_PAD_NANDF_D15__SD3_DAT7 = IOMUX_PAD(0x53c, 0x154, 5,
> __NA_, 0, MX51_SDHCI_PAD_CTRL),
> MX51_PAD_NANDF_D14__GPIO3_26 = IOMUX_PAD(0x540, 0x158, 3,
> __NA_, 0, MX51_GPIO_PAD_CTRL),
> MX51_PAD_NANDF_D14__PATA_DATA14 = IOMUX_PAD(0x540, 0x158, 1,
> __NA_, 0, NO_PAD_CTRL),
> + MX51_PAD_NANDF_D14__SD3_DAT6 = IOMUX_PAD(0x540, 0x158, 5,
> __NA_, 0, MX51_SDHCI_PAD_CTRL),
> MX51_PAD_NANDF_D13__GPIO3_27 = IOMUX_PAD(0x544, 0x15c, 3,
> __NA_, 0, MX51_GPIO_PAD_CTRL),
> MX51_PAD_NANDF_D13__PATA_DATA13 = IOMUX_PAD(0x544, 0x15c, 1,
> __NA_, 0, NO_PAD_CTRL),
> + MX51_PAD_NANDF_D13__SD3_DAT5 = IOMUX_PAD(0x544, 0x15c, 5,
> __NA_, 0, MX51_SDHCI_PAD_CTRL),
> MX51_PAD_NANDF_D12__PATA_DATA12 = IOMUX_PAD(0x548, 0x160, 1,
> __NA_, 0, NO_PAD_CTRL),
> + MX51_PAD_NANDF_D12__SD3_DAT4 = IOMUX_PAD(0x548, 0x160, 5,
> __NA_, 0, MX51_SDHCI_PAD_CTRL),
> MX51_PAD_NANDF_D11__FEC_RX_DV = IOMUX_PAD(0x54c, 0x164, 2,
> 0x96c, 0, NO_PAD_CTRL),
> MX51_PAD_NANDF_D11__PATA_DATA11 = IOMUX_PAD(0x54c, 0x164, 1,
> __NA_, 0, NO_PAD_CTRL),
> MX51_PAD_NANDF_D10__GPIO3_30 = IOMUX_PAD(0x550, 0x168, 3,
> __NA_, 0, MX51_GPIO_PAD_CTRL),
> MX51_PAD_NANDF_D10__PATA_DATA10 = IOMUX_PAD(0x550, 0x168, 1,
> __NA_, 0, NO_PAD_CTRL),
> + MX51_PAD_NANDF_D10__SD3_DATA2 = IOMUX_PAD(0x550, 0x168, 5,
> 0x944, 1, MX51_SDHCI_PAD_CTRL),
> MX51_PAD_NANDF_D9__FEC_RDATA0 = IOMUX_PAD(0x554, 0x16c, 0x12,
> 0x958, 0, MX51_PAD_CTRL_4),
> MX51_PAD_NANDF_D9__GPIO3_31 = IOMUX_PAD(0x554, 0x16c, 3,
> __NA_, 0, MX51_GPIO_PAD_CTRL),
> MX51_PAD_NANDF_D9__PATA_DATA9 = IOMUX_PAD(0x554, 0x16c, 1,
> __NA_, 0, NO_PAD_CTRL),
> + MX51_PAD_NANDF_D9__SD3_DATA1 = IOMUX_PAD(0x554, 0x16c, 5,
> 0x940, 1, MX51_SDHCI_PAD_CTRL),
> MX51_PAD_NANDF_D8__FEC_TDATA0 = IOMUX_PAD(0x558, 0x170, 2,
> __NA_, 0, MX51_PAD_CTRL_5),
> MX51_PAD_NANDF_D8__PATA_DATA8 = IOMUX_PAD(0x558, 0x170, 1,
> __NA_, 0, NO_PAD_CTRL),
> + MX51_PAD_NANDF_D8__SD3_DATA0 = IOMUX_PAD(0x558, 0x170, 5,
> 0x93c, 1, MX51_SDHCI_PAD_CTRL),
> MX51_PAD_NANDF_D7__PATA_DATA7 = IOMUX_PAD(0x55c, 0x174, 1,
> __NA_, 0, NO_PAD_CTRL),
> MX51_PAD_NANDF_D6__PATA_DATA6 = IOMUX_PAD(0x560, 0x178, 1,
> __NA_, 0, NO_PAD_CTRL),
> MX51_PAD_NANDF_D5__PATA_DATA5 = IOMUX_PAD(0x564, 0x17c, 1,
> __NA_, 0, NO_PAD_CTRL),
> @@ -147,6 +158,7 @@ enum {
> MX51_PAD_NANDF_D2__PATA_DATA2 = IOMUX_PAD(0x570, 0x188, 1,
> __NA_, 0, NO_PAD_CTRL),
> MX51_PAD_NANDF_D1__PATA_DATA1 = IOMUX_PAD(0x574, 0x18c, 1,
> __NA_, 0, NO_PAD_CTRL),
> MX51_PAD_NANDF_D0__PATA_DATA0 = IOMUX_PAD(0x578, 0x190, 1,
> __NA_, 0, NO_PAD_CTRL),
> + MX51_PAD_CSI1_VSYNC__GPIO3_14 = IOMUX_PAD(0x5ac, 0x1c4, 3,
> __NA_, 0, MX51_GPIO_PAD_CTRL),
> MX51_PAD_CSI2_D12__GPIO4_9 = IOMUX_PAD(0x5bc, 0x1cc, 3,
> __NA_, 0, MX51_GPIO_PAD_CTRL),
> MX51_PAD_CSI2_D13__GPIO4_10 = IOMUX_PAD(0x5c0, 0x1d0, 3,
> __NA_, 0, MX51_GPIO_PAD_CTRL),
> MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI = IOMUX_PAD(0x600, 0x210, 0,
> __NA_, 0, MX51_ECSPI_PAD_CTRL),
> @@ -185,7 +197,13 @@ enum {
> MX51_PAD_DI1_PIN3__DI1_PIN3 = IOMUX_PAD(0x72c, 0x32c, 0,
> __NA_, 0, NO_PAD_CTRL),
> MX51_PAD_DI1_PIN2__DI1_PIN2 = IOMUX_PAD(0x734, 0x330, 0,
> __NA_, 0, NO_PAD_CTRL),
> MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK = IOMUX_PAD(0x754, 0x34c, 0,
> __NA_, 0, NO_PAD_CTRL),
> + MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 = IOMUX_PAD(0x754, 0x34c, 2,
> 0x95c, 1, NO_PAD_CTRL),
> + MX51_PAD_DI_GP4__FEC_RDATA2 = IOMUX_PAD(0x758, 0x350, 2,
> 0x960, 1, NO_PAD_CTRL),
> MX51_PAD_DI_GP4__DI2_PIN15 = IOMUX_PAD(0x758, 0x350, 4,
> __NA_, 0, NO_PAD_CTRL),
> + MX51_PAD_DISP2_DAT9__FEC_TX_EN = IOMUX_PAD(0x780, 0x378, 2,
> __NA_, 0, PAD_CTL_DSE_HIGH),
> + MX51_PAD_DISP2_DAT13__FEC_TX_CLK = IOMUX_PAD(0x790, 0x388, 2,
> 0x974, 1, MX51_PAD_CTRL_2),
> + MX51_PAD_DISP2_DAT14__FEC_RDATA0 = IOMUX_PAD(0x794, 0x38c, 2,
> 0x958, 1, NO_PAD_CTRL),
> + MX51_PAD_DISP2_DAT15__FEC_TDATA0 = IOMUX_PAD(0x798, 0x390, 2,
> __NA_, 0, PAD_CTL_DSE_HIGH),
> MX51_PAD_SD1_CMD__SD1_CMD = IOMUX_PAD(0x79c, 0x394, 0x10,
> __NA_, 0, MX51_SDHCI_PAD_CTRL),
> MX51_PAD_SD1_CLK__SD1_CLK = IOMUX_PAD(0x7a0, 0x398, 0x10,
> __NA_, 0, MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS),
> MX51_PAD_SD1_DATA0__SD1_DATA0 = IOMUX_PAD(0x7a4, 0x39c, 0x10,
> __NA_, 0, MX51_SDHCI_PAD_CTRL),
> @@ -195,6 +213,7 @@ enum {
> MX51_PAD_GPIO1_0__GPIO1_0 = IOMUX_PAD(0x7b4, 0x3ac, 1,
> __NA_, 0, MX51_GPIO_PAD_CTRL),
> MX51_PAD_GPIO1_0__SD1_CD = IOMUX_PAD(0x7b4, 0x3ac, 0,
> __NA_, 0, MX51_ESDHC_PAD_CTRL),
> MX51_PAD_GPIO1_1__SD1_WP = IOMUX_PAD(0x7b8, 0x3b0, 0,
> __NA_, 0, MX51_ESDHC_PAD_CTRL),
> + MX51_PAD_GPIO1_1__GPIO1_1 = IOMUX_PAD(0x7b8, 0x3b0, 1,
> __NA_, 0, MX51_GPIO_PAD_CTRL),
> MX51_PAD_SD2_CMD__SD2_CMD = IOMUX_PAD(0x7bc, 0x3b4, 0x10,
> __NA_, 0, MX51_SDHCI_PAD_CTRL),
> MX51_PAD_SD2_CLK__SD2_CLK = IOMUX_PAD(0x7c0, 0x3b8, 0x10,
> __NA_, 0, MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS),
> MX51_PAD_SD2_DATA0__SD2_DATA0 = IOMUX_PAD(0x7c4, 0x3bc, 0x10,
> __NA_, 0, MX51_SDHCI_PAD_CTRL),
> diff --git a/arch/arm/include/asm/mach-types.h
> b/arch/arm/include/asm/mach-types.h
> index d4a447b..b8f0a6a 100644
> --- a/arch/arm/include/asm/mach-types.h
> +++ b/arch/arm/include/asm/mach-types.h
> @@ -1103,6 +1103,7 @@ extern unsigned int __machine_arch_type;
> #define MACH_TYPE_THALES_ADC 3492
> #define MACH_TYPE_UBISYS_P9D_EVP 3493
> #define MACH_TYPE_ATDGP318 3494
> +#define MACH_TYPE_MX51_NA04 3719
> #define MACH_TYPE_OMAP5_SEVM 3777
> #define MACH_TYPE_ARMADILLO_800EVA 3863
> #define MACH_TYPE_KZM9G 4140
> @@ -14201,6 +14202,18 @@ extern unsigned int __machine_arch_type;
> # define machine_is_atdgp318() (0)
> #endif
Dop this. We do not use it anymore. You can set directly your mach
number into mx51_na04.h.
>
> +#ifdef CONFIG_MACH_MX51_NA04
> +# ifdef machine_arch_type
> +# undef machine_arch_type
> +# define machine_arch_type __machine_arch_type
> +# else
> +# define machine_arch_type MACH_TYPE_MX51_NA04
> +# endif
> +# define machine_is_mx51_na04() (machine_arch_type ==
> MACH_TYPE_MX51_NA04)
> +#else
> +# define machine_is_mx51_na04() (0)
> +#endif
> +
> #ifdef CONFIG_MACH_OMAP5_SEVM
> # ifdef machine_arch_type
> # undef machine_arch_type
> diff --git a/board/hercules/mx51_na04/Kconfig
> b/board/hercules/mx51_na04/Kconfig
> new file mode 100644
> index 0000000..8214328
> --- /dev/null
> +++ b/board/hercules/mx51_na04/Kconfig
> @@ -0,0 +1,15 @@
> +if TARGET_MX51_NA04
> +
> +config SYS_BOARD
> + default "mx51_na04"
> +
> +config SYS_VENDOR
> + default "hercules"
> +
> +config SYS_SOC
> + default "mx5"
> +
> +config SYS_CONFIG_NAME
> + default "mx51_na04"
> +
> +endif
> diff --git a/board/hercules/mx51_na04/MAINTAINERS
> b/board/hercules/mx51_na04/MAINTAINERS
> new file mode 100644
> index 0000000..7825f76
> --- /dev/null
> +++ b/board/hercules/mx51_na04/MAINTAINERS
> @@ -0,0 +1,6 @@
> +MX51_NA04 BOARD
> +M: Emil Renner Berthing <u-b...@esmil.dk>
> +S: Maintained
> +F: board/hercules/mx51_na04/
> +F: include/configs/mx51_na04.h
> +F: configs/mx51_na04_defconfig
> diff --git a/board/hercules/mx51_na04/Makefile
> b/board/hercules/mx51_na04/Makefile
> new file mode 100644
> index 0000000..d7d2aa7
> --- /dev/null
> +++ b/board/hercules/mx51_na04/Makefile
> @@ -0,0 +1,10 @@
> +#
> +# Copyright (C) 2014, Emil Renner Berthing <u-b...@esmil.dk>
> +# Copyright (C) 2007, Guennadi Liakhovetski <l...@denx.de>
> +#
> +# (C) Copyright 2009 Freescale Semiconductor, Inc.
> +#
> +# SPDX-License-Identifier: GPL-2.0+
> +#
> +
> +obj-y += mx51_na04.o
> diff --git a/board/hercules/mx51_na04/mx51_na04.c
> b/board/hercules/mx51_na04/mx51_na04.c
> new file mode 100644
> index 0000000..c573791
> --- /dev/null
> +++ b/board/hercules/mx51_na04/mx51_na04.c
> @@ -0,0 +1,469 @@
> +/*
> + * (C) Copyright 2014 Emil Renner Berthing <u-b...@esmil.dk>
> + * (C) Copyright 2009 Freescale Semiconductor, Inc.
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#include <common.h>
> +#include <asm/io.h>
> +#include <asm/gpio.h>
> +#include <asm/arch/imx-regs.h>
> +#include <asm/arch/iomux-mx51.h>
> +#include <asm/errno.h>
> +#include <asm/arch/sys_proto.h>
> +#include <asm/arch/crm_regs.h>
> +#include <asm/arch/clock.h>
> +#include <i2c.h>
> +#include <mmc.h>
> +#include <fsl_esdhc.h>
> +#include <power/pmic.h>
> +#include <fsl_pmic.h>
> +#include <mc13892.h>
> +#include <usb/ehci-fsl.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +#define UART_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN |
> PAD_CTL_DSE_HIGH)
> +
> +static const iomux_v3_cfg_t mx51_na04_pads[] = {
> + /* LCD */
> +#define MX51_NA04_LCD_3V3 IMX_GPIO_NR(4, 9)
> + MX51_PAD_CSI2_D12__GPIO4_9,
> +#define MX51_NA04_LVDS_POWER IMX_GPIO_NR(3, 3)
> + MX51_PAD_DI1_D0_CS__GPIO3_3,
> +#define MX51_NA04_BACKLIGHT_CTL IMX_GPIO_NR(3, 4)
> + MX51_PAD_DI1_D1_CS__GPIO3_4,
> +#define MX51_NA04_BACKLIGHT_PWM IMX_GPIO_NR(1, 2)
> + MX51_PAD_GPIO1_2__GPIO1_2,
> +
> + /* UART 1 */
> + MX51_PAD_UART1_RXD__UART1_RXD,
> + MX51_PAD_UART1_TXD__UART1_TXD,
> + NEW_PAD_CTRL(MX51_PAD_UART1_RTS__UART1_RTS, UART_PAD_CTRL),
> + NEW_PAD_CTRL(MX51_PAD_UART1_CTS__UART1_CTS, UART_PAD_CTRL),
> +
> +#ifdef CONFIG_FEC_MXC
> + /* FEC Ethernet */
> + NEW_PAD_CTRL(MX51_PAD_EIM_EB2__FEC_MDIO, PAD_CTL_HYS |
> + PAD_CTL_PUS_22K_UP | PAD_CTL_ODE |
> + PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST),
> + MX51_PAD_NANDF_CS3__FEC_MDC,
> + NEW_PAD_CTRL(MX51_PAD_EIM_CS3__FEC_RDATA3,
> + MX51_PAD_CTRL_2),
> + NEW_PAD_CTRL(MX51_PAD_DI_GP4__FEC_RDATA2,
> + MX51_PAD_CTRL_2),
> + NEW_PAD_CTRL(MX51_PAD_DI2_DISP_CLK__FEC_RDATA1,
> + MX51_PAD_CTRL_2),
> + NEW_PAD_CTRL(MX51_PAD_DISP2_DAT14__FEC_RDATA0,
> + MX51_PAD_CTRL_2),
> + MX51_PAD_NANDF_CS6__FEC_TDATA3,
> + MX51_PAD_NANDF_CS5__FEC_TDATA2,
> + MX51_PAD_NANDF_CS4__FEC_TDATA1,
> + MX51_PAD_DISP2_DAT15__FEC_TDATA0,
> + MX51_PAD_DISP2_DAT9__FEC_TX_EN,
> + MX51_PAD_NANDF_CS2__FEC_TX_ER,
> + MX51_PAD_DISP2_DAT13__FEC_TX_CLK,
> + NEW_PAD_CTRL(MX51_PAD_NANDF_RB2__FEC_COL,
> + MX51_PAD_CTRL_4),
> + NEW_PAD_CTRL(MX51_PAD_NANDF_RB3__FEC_RX_CLK,
> + MX51_PAD_CTRL_4),
> + MX51_PAD_EIM_CS5__FEC_CRS,
> + MX51_PAD_EIM_CS4__FEC_RX_ER,
> + NEW_PAD_CTRL(MX51_PAD_NANDF_D11__FEC_RX_DV,
> + MX51_PAD_CTRL_4),
> +#define MX51_NA04_PHY_RESET IMX_GPIO_NR(2, 14)
> + NEW_PAD_CTRL(MX51_PAD_EIM_A20__GPIO2_14, PAD_CTL_PUE),
> +#endif
> +
> +#ifdef CONFIG_MXC_SPI
> + /* SPI 1 */
> + NEW_PAD_CTRL(MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI, PAD_CTL_HYS |
> + PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST),
> + NEW_PAD_CTRL(MX51_PAD_CSPI1_MISO__ECSPI1_MISO, PAD_CTL_HYS |
> + PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST),
> + NEW_PAD_CTRL(MX51_PAD_CSPI1_SS1__ECSPI1_SS1,
> + MX51_GPIO_PAD_CTRL),
> + MX51_PAD_CSPI1_SS0__ECSPI1_SS0,
> + NEW_PAD_CTRL(MX51_PAD_CSPI1_RDY__ECSPI1_RDY, MX51_PAD_CTRL_2),
> + NEW_PAD_CTRL(MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK, PAD_CTL_HYS |
> + PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST),
> +#endif
> +
> + /* USB Host 1 */
> + MX51_PAD_USBH1_CLK__USBH1_CLK,
> + MX51_PAD_USBH1_DIR__USBH1_DIR,
> + MX51_PAD_USBH1_STP__USBH1_STP,
> + MX51_PAD_USBH1_NXT__USBH1_NXT,
> + MX51_PAD_USBH1_DATA0__USBH1_DATA0,
> + MX51_PAD_USBH1_DATA1__USBH1_DATA1,
> + MX51_PAD_USBH1_DATA2__USBH1_DATA2,
> + MX51_PAD_USBH1_DATA3__USBH1_DATA3,
> + MX51_PAD_USBH1_DATA4__USBH1_DATA4,
> + MX51_PAD_USBH1_DATA5__USBH1_DATA5,
> + MX51_PAD_USBH1_DATA6__USBH1_DATA6,
> + MX51_PAD_USBH1_DATA7__USBH1_DATA7,
> +#define MX51_NA04_USB_PHY_RESET IMX_GPIO_NR(2, 5)
> + MX51_PAD_EIM_D21__GPIO2_5,
> +#define MX51_NA04_USB_CLK_EN_B IMX_GPIO_NR(2, 27)
> + MX51_PAD_EIM_CS2__GPIO2_27,
> +#define MX51_NA04_USBH1_HUB_RST IMX_GPIO_NR(1, 6)
> + NEW_PAD_CTRL(MX51_PAD_GPIO1_6__GPIO1_6, 0),
> +
> + /* Power Key */
> +#define MX51_NA04_POWER_KEY IMX_GPIO_NR(2, 21)
> + NEW_PAD_CTRL(MX51_PAD_EIM_A27__GPIO2_21, PAD_CTL_HYS),
> +
> + /* Battery LED */
> +#define MX51_NA04_BATTERY_LED IMX_GPIO_NR(3, 14)
> + NEW_PAD_CTRL(MX51_PAD_CSI1_VSYNC__GPIO3_14,
> + PAD_CTL_SRE_FAST),
> +};
> +
> +int dram_init(void)
> +{
> + /* dram_init must store complete ramsize in gd->ram_size */
> + gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
> + PHYS_SDRAM_1_SIZE);
> + return 0;
> +}
> +
> +u32 get_board_rev(void)
> +{
> + u32 rev = get_cpu_rev();
> + if (!gpio_get_value(IMX_GPIO_NR(1, 22)))
> + rev |= BOARD_REV_2_0 << BOARD_VER_OFFSET;
> + return rev;
> +}
> +
> +static void init_lcd(void)
> +{
> + /* Blank the LCD */
> + gpio_direction_output(MX51_NA04_LVDS_POWER, 0);
> + gpio_direction_output(MX51_NA04_BACKLIGHT_CTL, 0);
> + gpio_direction_output(MX51_NA04_BACKLIGHT_PWM, 0);
> +
> + /* ..but keep the power on to avoid a nasty
> + * white flash when Linux takes over */
Multi-line comment style, please fix it.
> + gpio_direction_output(MX51_NA04_LCD_3V3, 1);
> +}
> +
> +static void reset_usb(void)
> +{
> + /* Turn off USB_CLK_EN_B line */
> + gpio_direction_output(MX51_NA04_USB_CLK_EN_B, 1);
> +
> + /* Assert USB hub reset */
> + gpio_direction_output(MX51_NA04_USBH1_HUB_RST, 0);
> +
> + /* Assert USB phy reset */
> + gpio_direction_output(MX51_NA04_USB_PHY_RESET, 0);
> +}
> +
> +#ifdef CONFIG_USB_EHCI_MX5
> +int board_ehci_hcd_init(int port)
> +{
> + /* De-assert USB phy reset */
> + gpio_set_value(MX51_NA04_USB_PHY_RESET, 1);
> +
> + /* Drive USB_CLK_EN_B line low */
> + gpio_direction_output(MX51_NA04_USB_CLK_EN_B, 0);
> +
> + mdelay(2);
> +
> + /* De-assert USB usb reset */
> + gpio_set_value(MX51_NA04_USBH1_HUB_RST, 1);
> + return 0;
> +}
> +#endif
> +
> +#ifdef CONFIG_MXC_SPI
I know this comes from other board, but if your board has always the
PMIC, CONFIG_MXC_SPI must simply be set, and you could drop the #ifdef here.
> +static void power_init(void)
> +{
> + unsigned int val;
> + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE;
> + struct pmic *p;
> + int ret;
> +
> + ret = pmic_init(CONFIG_FSL_PMIC_BUS);
> + if (ret)
> + return;
> +
> + p = pmic_get("FSL_PMIC");
> + if (!p)
> + return;
> +
> + /* Write needed to Power Gate 2 register */
> + pmic_reg_read(p, REG_POWER_MISC, &val);
> + val &= ~PWGT2SPIEN;
> + pmic_reg_write(p, REG_POWER_MISC, val);
> +
> + /* Externally powered */
> + pmic_reg_read(p, REG_CHARGE, &val);
> + val |= ICHRG0 | ICHRG1 | ICHRG2 | ICHRG3 | CHGAUTOB;
> + pmic_reg_write(p, REG_CHARGE, val);
> +
> + /* power up the system first */
> + pmic_reg_write(p, REG_POWER_MISC, PWUP);
> +
> + /* Set core voltage to 1.1V */
> + pmic_reg_read(p, REG_SW_0, &val);
> + val = (val & ~SWx_VOLT_MASK) | SWx_1_100V;
> + pmic_reg_write(p, REG_SW_0, val);
> +
> + /* Setup VCC (SW2) to 1.25 */
> + pmic_reg_read(p, REG_SW_1, &val);
> + val = (val & ~SWx_VOLT_MASK) | SWx_1_250V;
> + pmic_reg_write(p, REG_SW_1, val);
> +
> + /* Setup 1V2_DIG1 (SW3) to 1.25 */
> + pmic_reg_read(p, REG_SW_2, &val);
> + val = (val & ~SWx_VOLT_MASK) | SWx_1_250V;
> + pmic_reg_write(p, REG_SW_2, val);
> + udelay(50);
> +
> + /* Raise the core frequency to 800MHz */
> + writel(0x0, &mxc_ccm->cacrr);
> +
> + /* Set switchers in Auto in NORMAL mode & STANDBY mode */
> + /* Setup the switcher mode for SW1 & SW2*/
Multiline comment - please fix it globally.
> + pmic_reg_read(p, REG_SW_4, &val);
> + val = (val & ~((SWMODE_MASK << SWMODE1_SHIFT) |
> + (SWMODE_MASK << SWMODE2_SHIFT)));
> + val |= (SWMODE_AUTO_AUTO << SWMODE1_SHIFT) |
> + (SWMODE_AUTO_AUTO << SWMODE2_SHIFT);
> + pmic_reg_write(p, REG_SW_4, val);
> +
> + /* Setup the switcher mode for SW3 & SW4 */
> + pmic_reg_read(p, REG_SW_5, &val);
> + val = (val & ~((SWMODE_MASK << SWMODE3_SHIFT) |
> + (SWMODE_MASK << SWMODE4_SHIFT)));
> + val |= (SWMODE_AUTO_AUTO << SWMODE3_SHIFT) |
> + (SWMODE_AUTO_AUTO << SWMODE4_SHIFT);
> + pmic_reg_write(p, REG_SW_5, val);
> +
> + /* Set VDIG to 1.65V, VGEN3 to 1.8V, VCAM to 2.6V */
> + pmic_reg_read(p, REG_SETTING_0, &val);
> + val &= ~(VCAM_MASK | VGEN3_MASK | VDIG_MASK);
> + val |= VDIG_1_65 | VGEN3_1_8 | VCAM_2_6;
> + pmic_reg_write(p, REG_SETTING_0, val);
> +
> + /* Set VVIDEO to 2.775V, VAUDIO to 3V, VSD to 3.15V */
> + pmic_reg_read(p, REG_SETTING_1, &val);
> + val &= ~(VVIDEO_MASK | VSD_MASK | VAUDIO_MASK);
> + val |= VSD_3_15 | VAUDIO_3_0 | VVIDEO_2_775;
> + pmic_reg_write(p, REG_SETTING_1, val);
> +
> + /* Configure VGEN3 and VCAM regulators to use external PNP */
> + val = VGEN3CONFIG | VCAMCONFIG;
> + pmic_reg_write(p, REG_MODE_1, val);
> + udelay(200);
> +
> + /* Enable VGEN3, VCAM, VAUDIO, VVIDEO, VSD regulators */
> + val = VGEN3EN | VGEN3CONFIG | VCAMEN | VCAMCONFIG |
> + VVIDEOEN | VAUDIOEN | VSDEN;
> + pmic_reg_write(p, REG_MODE_1, val);
> +}
> +#else
> +static inline void power_init(void) {}
> +#endif
> +
> +#ifdef CONFIG_FEC_MXC
> +static void reset_fec(void)
> +{
> + gpio_direction_output(MX51_NA04_PHY_RESET, 0);
> + udelay(500);
> + gpio_set_value(MX51_NA04_PHY_RESET, 1);
> +}
> +#else
> +static inline void reset_fec(void) {}
> +#endif
> +
> +#ifdef CONFIG_FSL_ESDHC
> +int board_mmc_init(bd_t *bis)
> +{
> + static const iomux_v3_cfg_t sd1_pads[] = {
> + NEW_PAD_CTRL(MX51_PAD_SD1_CMD__SD1_CMD,
> + PAD_CTL_DSE_MAX | PAD_CTL_HYS |
> + PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
> + NEW_PAD_CTRL(MX51_PAD_SD1_CLK__SD1_CLK,
> + PAD_CTL_DSE_MAX |
> + PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
> + NEW_PAD_CTRL(MX51_PAD_SD1_DATA0__SD1_DATA0,
> + PAD_CTL_DSE_MAX | PAD_CTL_HYS |
> + PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
> + NEW_PAD_CTRL(MX51_PAD_SD1_DATA1__SD1_DATA1,
> + PAD_CTL_DSE_MAX | PAD_CTL_HYS |
> + PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
> + NEW_PAD_CTRL(MX51_PAD_SD1_DATA2__SD1_DATA2,
> + PAD_CTL_DSE_MAX | PAD_CTL_HYS |
> + PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
> + NEW_PAD_CTRL(MX51_PAD_SD1_DATA3__SD1_DATA3,
> + PAD_CTL_DSE_MAX | PAD_CTL_HYS |
> + PAD_CTL_PUS_100K_DOWN | PAD_CTL_SRE_FAST),
> +#define MX51_NA04_SDHC1_CD IMX_GPIO_NR(1, 0)
> + NEW_PAD_CTRL(MX51_PAD_GPIO1_0__GPIO1_0, PAD_CTL_HYS),
> +#define MX51_NA04_SDHC1_WP IMX_GPIO_NR(1, 1)
> + NEW_PAD_CTRL(MX51_PAD_GPIO1_1__GPIO1_1, PAD_CTL_HYS),
> + };
> +
> + static const iomux_v3_cfg_t sd2_pads[] = {
> + NEW_PAD_CTRL(MX51_PAD_SD2_CMD__SD2_CMD,
> + PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
> + NEW_PAD_CTRL(MX51_PAD_SD2_CLK__SD2_CLK,
> + PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
> + NEW_PAD_CTRL(MX51_PAD_SD2_DATA0__SD2_DATA0,
> + PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
> + NEW_PAD_CTRL(MX51_PAD_SD2_DATA1__SD2_DATA1,
> + PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
> + NEW_PAD_CTRL(MX51_PAD_SD2_DATA2__SD2_DATA2,
> + PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
> + NEW_PAD_CTRL(MX51_PAD_SD2_DATA3__SD2_DATA3,
> + PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
> +#define MX51_NA04_SDHC2_CD IMX_GPIO_NR(1, 7)
> + NEW_PAD_CTRL(MX51_PAD_GPIO1_7__GPIO1_7, PAD_CTL_HYS),
> +#define MX51_NA04_SDHC2_WP IMX_GPIO_NR(1, 5)
> + NEW_PAD_CTRL(MX51_PAD_GPIO1_5__GPIO1_5, PAD_CTL_HYS),
> + };
> +
> + static const iomux_v3_cfg_t sd3_pads[] = {
> + NEW_PAD_CTRL(MX51_PAD_NANDF_RDY_INT__SD3_CMD,
> + PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
> + NEW_PAD_CTRL(MX51_PAD_NANDF_CS7__SD3_CLK,
> + PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
> + NEW_PAD_CTRL(MX51_PAD_NANDF_D8__SD3_DATA0,
> + PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
> + NEW_PAD_CTRL(MX51_PAD_NANDF_D9__SD3_DATA1,
> + PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
> + NEW_PAD_CTRL(MX51_PAD_NANDF_D10__SD3_DATA2,
> + PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
> + NEW_PAD_CTRL(MX51_PAD_NANDF_RB0__SD3_DATA3,
> + PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
> + NEW_PAD_CTRL(MX51_PAD_NANDF_D12__SD3_DAT4,
> + PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
> + NEW_PAD_CTRL(MX51_PAD_NANDF_D13__SD3_DAT5,
> + PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
> + NEW_PAD_CTRL(MX51_PAD_NANDF_D14__SD3_DAT6,
> + PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
> + NEW_PAD_CTRL(MX51_PAD_NANDF_D15__SD3_DAT7,
> + PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
> + };
> +
> + static struct fsl_esdhc_cfg esdhc_cfg[] = {
> + {
> + .esdhc_base = MMC_SDHC1_BASE_ADDR,
> + .max_bus_width = 4,
> + },
> + {
> + .esdhc_base = MMC_SDHC2_BASE_ADDR,
> + .max_bus_width = 4,
> + },
> + {
> + .esdhc_base = MMC_SDHC3_BASE_ADDR,
> + .max_bus_width = 8,
> + },
> + };
> + u32 index;
> + int ret;
> +
> + for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) {
> + switch (index) {
> + case 0:
> + imx_iomux_v3_setup_multiple_pads(sd1_pads,
> + ARRAY_SIZE(sd1_pads));
> + gpio_direction_input(MX51_NA04_SDHC1_CD);
> + gpio_direction_input(MX51_NA04_SDHC1_WP);
> + esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
> + break;
> + case 1:
> + imx_iomux_v3_setup_multiple_pads(sd2_pads,
> + ARRAY_SIZE(sd2_pads));
> + gpio_direction_input(MX51_NA04_SDHC2_CD);
> + gpio_direction_input(MX51_NA04_SDHC2_WP);
> + esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
> + break;
> + case 2:
> + imx_iomux_v3_setup_multiple_pads(sd3_pads,
> + ARRAY_SIZE(sd3_pads));
> + esdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
> + break;
> + default:
> + printf("Warning: you configured more ESDHC
> controllers(%d) than supported by the board(3)\n",
> + CONFIG_SYS_FSL_ESDHC_NUM);
> + return -EINVAL;
> + }
> + ret = fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
> + if (ret)
> + return ret;
> + }
> + return 0;
> +}
> +
> +int board_mmc_getcd(struct mmc *mmc)
> +{
> + struct fsl_esdhc_cfg *cfg = mmc->priv;
> +
> + switch (cfg->esdhc_base) {
> + case MMC_SDHC1_BASE_ADDR:
> + return !gpio_get_value(MX51_NA04_SDHC1_CD);
> + case MMC_SDHC2_BASE_ADDR:
> + return !gpio_get_value(MX51_NA04_SDHC2_CD);
> + case MMC_SDHC3_BASE_ADDR:
> + return 1;
> + }
> +
> + return 0;
> +}
> +
> +int board_mmc_getwp(struct mmc *mmc)
> +{
> + struct fsl_esdhc_cfg *cfg = mmc->priv;
> +
> + switch (cfg->esdhc_base) {
> + case MMC_SDHC1_BASE_ADDR:
> + return !!gpio_get_value(MX51_NA04_SDHC1_WP);
> + case MMC_SDHC2_BASE_ADDR:
> + return !!gpio_get_value(MX51_NA04_SDHC2_WP);
> + case MMC_SDHC3_BASE_ADDR:
> + return 0;
> + }
> +
> + return 0;
> +}
> +#endif
> +
> +int board_early_init_f(void)
> +{
> + imx_iomux_v3_setup_multiple_pads(mx51_na04_pads,
> + ARRAY_SIZE(mx51_na04_pads));
> + init_lcd();
> +
> + return 0;
> +}
> +
> +int board_init(void)
> +{
> + /* Address of boot parameters */
> + gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
> +
> + gpio_direction_input(MX51_NA04_POWER_KEY);
> + gpio_direction_output(MX51_NA04_BATTERY_LED, 0);
> + reset_usb();
> +
> + return 0;
> +}
> +
> +int board_late_init(void)
> +{
> + power_init();
> + reset_fec();
> +
> + return 0;
> +}
> +
> +int checkboard(void)
> +{
> + puts("Board: Hercules eCAFE Slim/EX HD\n");
> +
> + return 0;
> +}
> diff --git a/configs/mx51_na04_defconfig b/configs/mx51_na04_defconfig
> new file mode 100644
> index 0000000..eff61c2
> --- /dev/null
> +++ b/configs/mx51_na04_defconfig
> @@ -0,0 +1,3 @@
> +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx51evk/imximage.cfg"
> +CONFIG_ARM=y
> +CONFIG_TARGET_MX51_NA04=y
> diff --git a/include/configs/mx51_na04.h b/include/configs/mx51_na04.h
> new file mode 100644
> index 0000000..70e7fc2
> --- /dev/null
> +++ b/include/configs/mx51_na04.h
> @@ -0,0 +1,246 @@
> +/*
> + * Copyright (C) 2014, Emil Renner Berthing <u-b...@esmil.dk>
> + * Copyright (C) 2007, Guennadi Liakhovetski <l...@denx.de>
> + *
> + * (C) Copyright 2009 Freescale Semiconductor, Inc.
> + *
> + * Configuration settings for the Hercules eCAFE Slim/EX HD laptops.
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#ifndef __CONFIG_H
> +#define __CONFIG_H
> +
> + /* High Level Configuration Options */
> +
> +#define CONFIG_MX51 /* in a mx51 */
> +
> +#define CONFIG_DISPLAY_CPUINFO
> +#define CONFIG_DISPLAY_BOARDINFO
> +
You can add here CONFIG_MACH_TYPE <your number>
> +#define CONFIG_SYS_TEXT_BASE 0x97800000
> +
> +#include <asm/arch/imx-regs.h>
> +
> +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
> +#define CONFIG_SETUP_MEMORY_TAGS
> +#define CONFIG_INITRD_TAG
> +#define CONFIG_REVISION_TAG
> +#define CONFIG_SYS_GENERIC_BOARD
> +
> +#define CONFIG_OF_LIBFDT
> +
> +#define CONFIG_MACH_TYPE MACH_TYPE_MX51_NA04
> +/*
> + * Size of malloc() pool
> + */
> +#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
> +
> +#define CONFIG_BOARD_LATE_INIT
> +
> +/*
> + * Hardware drivers
> + */
> +#define CONFIG_FSL_IIM
> +#define CONFIG_CMD_FUSE
> +
> +#define CONFIG_MXC_UART
> +#define CONFIG_MXC_UART_BASE UART1_BASE
> +#define CONFIG_MXC_GPIO
> +
> +/*
> + * SPI Configs
> + * */
> +#define CONFIG_CMD_SPI
> +
> +#define CONFIG_MXC_SPI
> +
> +/* PMIC Controller */
> +#define CONFIG_POWER
> +#define CONFIG_POWER_SPI
> +#define CONFIG_POWER_FSL
> +#define CONFIG_FSL_PMIC_BUS 0
> +#define CONFIG_FSL_PMIC_CS 0
> +#define CONFIG_FSL_PMIC_CLK 2500000
> +#define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH)
> +#define CONFIG_FSL_PMIC_BITLEN 32
> +#define CONFIG_RTC_MC13XXX
> +
> +/*
> + * MMC Configs
> + */
> +#define CONFIG_FSL_ESDHC
> +#define CONFIG_SYS_FSL_ESDHC_ADDR MMC_SDHC1_BASE_ADDR
> +#define CONFIG_SYS_FSL_ESDHC_NUM 3
> +
> +#define CONFIG_MMC
> +
> +#define CONFIG_CMD_MMC
> +#define CONFIG_GENERIC_MMC
> +#define CONFIG_CMD_FAT
> +#define CONFIG_DOS_PARTITION
> +
> +/*
> + * Eth Configs
> + */
> +#define CONFIG_MII
> +
> +#define CONFIG_FEC_MXC
> +#define IMX_FEC_BASE FEC_BASE_ADDR
> +#define CONFIG_FEC_MXC_PHYADDR 0x1F
> +#define CONFIG_ETHPRIME "FEC0"
> +#define CONFIG_ARP_TIMEOUT 200UL
> +
> +#define CONFIG_CMD_PING
> +#define CONFIG_CMD_DHCP
> +#define CONFIG_CMD_MII
> +#define CONFIG_CMD_NET
> +
> +/* USB Configs */
> +#define CONFIG_CMD_USB
> +#define CONFIG_CMD_FAT
> +#define CONFIG_USB_EHCI
> +#define CONFIG_USB_EHCI_MX5
> +#define CONFIG_USB_STORAGE
> +#define CONFIG_MXC_USB_PORT 1
> +#define CONFIG_MXC_USB_PORTSC PORT_PTS_ULPI
> +#define CONFIG_MXC_USB_FLAGS MXC_EHCI_POWER_PINS_ENABLED
> +
> +/* allow to overwrite serial and ethaddr */
> +#define CONFIG_ENV_OVERWRITE
> +#define CONFIG_CONS_INDEX 1
> +#define CONFIG_BAUDRATE 115200
> +
> +/***********************************************************
> + * Command definition
> + ***********************************************************/
> +
> +#include <config_cmd_default.h>
> +#define CONFIG_CMD_BOOTZ
> +#undef CONFIG_CMD_IMLS
> +#ifndef CONFIG_FEC_MXC
> +#undef CONFIG_CMD_NET
> +#endif
> +
> +#define CONFIG_CMD_DATE
> +#define CONFIG_CMD_GPIO
> +#define CONFIG_CMD_INI
> +
> +#define CONFIG_BOOTDELAY 0
> +#define CONFIG_PREBOOT "if gpio i ${powerkey};then setenv
> bootdelay 1;fi"
> +
> +#define CONFIG_LOADADDR 0x92000000 /* loadaddr env var */
> +
> +#define CONFIG_EXTRA_ENV_SETTINGS \
> + "fdt_addr=0x91000000\0" \
> + "initrd_addr=0x93000000\0" \
> + "powerkey=53\0" \
> + "batteryled=78\0" \
> + "mmcdev=1\0" \
> + "mmcpart=1\0" \
> + "load=fatload\0" \
> + "section=default\0" \
> + "linux=zImage\0" \
> + "devicetree=imx51-na04.dtb\0" \
> + "options=console=ttymxc0,115200n8 console=tty1 root=/dev/mmcblk0p2 ro
> rootwait\0" \
> + "mmcinit=" \
> + "if ${load} mmc ${mmcdev}:${mmcpart} ${loadaddr} boot.ini;then
> " \
> + "ini '' ${loadaddr} ${filesize};" \
> + "ini ${section} ${loadaddr} ${filesize};" \
> + "fi\0" \
> + "mmcboot=" \
> + "setenv bootargs ${options};" \
> + "if ${load} mmc ${mmcdev}:${mmcpart} ${loadaddr} ${linux};then
> " \
> + "if test -n ${devicetree};then " \
> + "if ${load} mmc ${mmcdev}:${mmcpart}
> ${fdt_addr} ${devicetree};then " \
> + "if test -n ${initrd};then " \
> + "if ${load} mmc
> ${mmcdev}:${mmcpart} ${initrd_addr} ${initrd};then " \
> + "bootz ${loadaddr}
> ${initrd_addr} ${fdt_addr};" \
> + "fi;" \
> + "else " \
> + "bootz ${loadaddr} -
> ${fdt_addr};" \
> + "fi;" \
> + "fi;" \
> + "else " \
> + "if test -n ${initrd};then " \
> + "if ${load} mmc ${mmcdev}:${mmcpart}
> ${initrd_addr} ${initrd};then " \
> + "bootz ${loadaddr}
> ${initrd_addr};" \
> + "fi;" \
> + "else " \
> + "bootz ${loadaddr};" \
> + "fi;" \
> + "fi;" \
> + "fi\0" \
> + "error=" \
> + "while true;do " \
> + "gpio s ${batteryled};sleep 1;" \
> + "gpio c ${batteryled};sleep 1;" \
> + "done"
> +
> +#define CONFIG_BOOTCOMMAND \
> + "if gpio i ${powerkey};then " \
> + "gpio s ${batteryled};" \
> + "setenv section fallback;" \
> + "fi;" \
> + "setenv bootcmd run mmcboot;" \
> + "run mmcinit;" \
> + "run bootcmd;" \
> + "run error"
> +
> +/*
> + * Miscellaneous configurable options
> + */
> +#define CONFIG_SYS_LONGHELP /* undef to save memory */
> +#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
> +#define CONFIG_AUTO_COMPLETE
> +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
> +/* Print Buffer Size */
> +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) +
> 16)
> +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
> +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
> +
> +#define CONFIG_SYS_MEMTEST_START 0x90000000
> +#define CONFIG_SYS_MEMTEST_END 0x90010000
> +
> +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
> +
> +#define CONFIG_CMDLINE_EDITING
> +
> +/*-----------------------------------------------------------------------
> + * Physical Memory Map
> + */
> +#define CONFIG_NR_DRAM_BANKS 1
> +#define PHYS_SDRAM_1 CSD0_BASE_ADDR
> +#define PHYS_SDRAM_1_SIZE (512 * 1024 * 1024)
> +
> +#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1)
> +#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR)
> +#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE)
> +
> +#define CONFIG_BOARD_EARLY_INIT_F
> +
> +#define CONFIG_SYS_INIT_SP_OFFSET \
> + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
> +#define CONFIG_SYS_INIT_SP_ADDR \
> + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
> +
> +#define CONFIG_SYS_DDR_CLKSEL 0
> +#define CONFIG_SYS_CLKTL_CBCDR 0x59E35100
> +#define CONFIG_SYS_MAIN_PWR_ON
> +
> +/*-----------------------------------------------------------------------
> + * FLASH and environment organization
> + */
> +#define CONFIG_SYS_NO_FLASH
> +
> +#define CONFIG_ENV_SIZE (8 * 1024)
> +
> +#define CONFIG_ENV_IS_NOWHERE
> +#ifndef CONFIG_ENV_IS_NOWHERE
> +#define CONFIG_ENV_IS_IN_MMC
> +#define CONFIG_SYS_MMC_ENV_DEV 1
> +#define CONFIG_ENV_OFFSET (6 * 64 * 1024)
> +#endif
> +
> +#endif
>
Best regards,
Stefano Babic
--
=====================================================================
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de
=====================================================================
_______________________________________________
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
