On 11/24/2014 01:11 AM, Shengzhou Liu wrote: > Add support for Freescale T1024/T1023 SoC. > > The T1024 SoC includes the following function and features: > - Two 64-bit Power architecture e5500 cores, up to 1.4GHz > - private 256KB L2 cache each core and shared 256KB CoreNet platform cache > (CPC) > - 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving > support > - Data Path Acceleration Architecture (DPAA) incorporating acceleration > - Four MAC for 1G/2.5G/10G network interfaces (RGMII, SGMII, QSGMII, XFI) > - High-speed peripheral interfaces > - Three PCI Express 2.0 controllers > - Additional peripheral interfaces > - One SATA 2.0 controller > - Two USB 2.0 controllers with integrated PHY > - Enhanced secure digital host controller (SD/eSDHC/eMMC) > - Enhanced serial peripheral interface (eSPI) > - Four I2C controllers > - Four 2-pin UARTs or two 4-pin UARTs > - Integrated Flash Controller supporting NAND and NOR flash > - Two 8-channel DMA engines > - Multicore programmable interrupt controller (PIC) > - LCD interface (DIU) with 12 bit dual data rate > - QUICC Engine block supporting TDM, HDLC, and UART > - Deep Sleep power implementaion (wakeup from GPIO/Timer/Ethernet/USB) > - Support for hardware virtualization and partitioning enforcement > - QorIQ Platform's Trust Architecture 2.0 > > Differences between T1024 and T1023: > Feature T1024 T1023 > QUICC Engine: yes no > DIU: yes no > Deep Sleep: yes no > I2C controller: 4 3 > DDR: 64-bit 32-bit > IFC: 32-bit 28-bit > > Signed-off-by: Shengzhou Liu <shengzhou....@freescale.com> > --- > v2: add new serdes 0x135 and 0x119 in t1024_serdes.c >
Applied to u-boot-mpc85xx, awaiting upstream. York _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
