The odroid-xu3 board file sets up clocks that should have are setup by
the SPL/BL2, so that code should be redundant. Drop it and make the XU3
an smdk5420 variant like e.g. Peach pit/pi, that way the only
differences in the boards u-boot binary are purely due to configuration
changes, not code differences.
Signed-off-by: Sjoerd Simons <sjoerd.sim...@collabora.co.uk>
---
arch/arm/cpu/armv7/exynos/Kconfig | 1 -
board/samsung/odroid-xu3/Kconfig | 12 ----
board/samsung/odroid-xu3/MAINTAINERS | 6 --
board/samsung/odroid-xu3/Makefile | 7 --
board/samsung/odroid-xu3/odroid-xu3.c | 122 ----------------------------------
board/samsung/odroid-xu3/setup.h | 95 --------------------------
board/samsung/smdk5420/Kconfig | 13 ++++
7 files changed, 13 insertions(+), 243 deletions(-)
delete mode 100644 board/samsung/odroid-xu3/Kconfig
delete mode 100644 board/samsung/odroid-xu3/MAINTAINERS
delete mode 100644 board/samsung/odroid-xu3/Makefile
delete mode 100644 board/samsung/odroid-xu3/odroid-xu3.c
delete mode 100644 board/samsung/odroid-xu3/setup.h
diff --git a/arch/arm/cpu/armv7/exynos/Kconfig
b/arch/arm/cpu/armv7/exynos/Kconfig
index 16c9a0e..88017c7 100644
--- a/arch/arm/cpu/armv7/exynos/Kconfig
+++ b/arch/arm/cpu/armv7/exynos/Kconfig
@@ -69,7 +69,6 @@ source "board/samsung/universal_c210/Kconfig"
source "board/samsung/origen/Kconfig"
source "board/samsung/trats2/Kconfig"
source "board/samsung/odroid/Kconfig"
-source "board/samsung/odroid-xu3/Kconfig"
source "board/samsung/arndale/Kconfig"
source "board/samsung/smdk5250/Kconfig"
source "board/samsung/smdk5420/Kconfig"
diff --git a/board/samsung/odroid-xu3/Kconfig b/board/samsung/odroid-xu3/Kconfig
deleted file mode 100644
index 6159692..0000000
--- a/board/samsung/odroid-xu3/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_ODROID_XU3
-
-config SYS_BOARD
- default "odroid-xu3"
-
-config SYS_VENDOR
- default "samsung"
-
-config SYS_CONFIG_NAME
- default "odroid_xu3"
-
-endif
diff --git a/board/samsung/odroid-xu3/MAINTAINERS
b/board/samsung/odroid-xu3/MAINTAINERS
deleted file mode 100644
index 50cf928..0000000
--- a/board/samsung/odroid-xu3/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-ODROID-XU3 BOARD
-M: Hyungwon Hwang <human.hw...@samsung.com>
-S: Maintained
-F: board/samsung/odroid-xu3/
-F: include/configs/odroid_xu3.h
-F: configs/odroid-xu3_defconfig
diff --git a/board/samsung/odroid-xu3/Makefile
b/board/samsung/odroid-xu3/Makefile
deleted file mode 100644
index 85ae5c5..0000000
--- a/board/samsung/odroid-xu3/Makefile
+++ /dev/null
@@ -1,7 +0,0 @@
-#
-# Copyright (c) 2014 Samsung Electronics Co., Ltd. All rights reserved.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := odroid-xu3.o
diff --git a/board/samsung/odroid-xu3/odroid-xu3.c
b/board/samsung/odroid-xu3/odroid-xu3.c
deleted file mode 100644
index 8c54842..0000000
--- a/board/samsung/odroid-xu3/odroid-xu3.c
+++ /dev/null
@@ -1,122 +0,0 @@
-/*
- * Copyright (C) 2014 Samsung Electronics
- * Hyungwon Hwang <human.hw...@samsung.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/clock.h>
-#include "setup.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-unsigned int get_board_rev(void)
-{
- return 0;
-}
-
-int exynos_init(void)
-{
- return 0;
-}
-
-#ifdef CONFIG_BOARD_EARLY_INIT_F
-static int board_clock_init(void)
-{
- unsigned int set, clr, clr_src_cpu, clr_pll_con0;
- struct exynos5420_clock *clk = (struct exynos5420_clock *)
- samsung_get_base_clock();
- /*
- * CMU_CPU clocks src to MPLL
- * Bit values: 0 ; 1
- * MUX_APLL_SEL: FIN_PLL ; FOUT_APLL
- * MUX_CORE_SEL: MOUT_APLL ; SCLK_MPLL
- * MUX_HPM_SEL: MOUT_APLL ; SCLK_MPLL_USER_C
- * MUX_MPLL_USER_SEL_C: FIN_PLL ; SCLK_MPLL
- */
-
- /* Set CMU_CPU clocks src to OSCCLK */
- clr_src_cpu = MUX_APLL_SEL(1) | MUX_CORE_SEL(1);
- set = MUX_APLL_SEL(0) | MUX_CORE_SEL(1);
-
- clrsetbits_le32(&clk->src_cpu, clr_src_cpu, set);
-
- while (MUX_STAT_CPU_CHANGING(readl(&clk->mux_stat_cpu)))
- continue;
-
- /* Set APLL to 1200MHz */
- clr_pll_con0 = SDIV(7) | PDIV(63) | MDIV(1023) | FSEL(1) |
- PLL_ENABLE(1);
- set = SDIV(0) | PDIV(2) | MDIV(100) | PLL_ENABLE(1);
-
- clrsetbits_le32(&clk->apll_con0, clr_pll_con0, set);
-
- while (!(readl(&clk->apll_con0) & PLL_LOCKED_BIT))
- continue;
-
- /* Set CMU_CPU clocks src to APLL */
- set = MUX_APLL_SEL(1) | MUX_CORE_SEL(0);
- clrsetbits_le32(&clk->src_cpu, clr_src_cpu, set);
-
- while (MUX_STAT_CPU_CHANGING(readl(&clk->mux_stat_cpu)))
- continue;
-
- clr = ARM_RATIO(7) | CPUD_RATIO(7) | ATB_RATIO(7) |
- PCLK_DBG_RATIO(7) | APLL_RATIO(7) | ARM2_RATIO(7);
- set = ARM_RATIO(0) | CPUD_RATIO(2) | ATB_RATIO(5) |
- PCLK_DBG_RATIO(5) | APLL_RATIO(0) | ARM2_RATIO(0);
-
- clrsetbits_le32(&clk->div_cpu0, clr, set);
-
- while (readl(&clk->div_stat_cpu0) & DIV_STAT_CPU0_CHANGING)
- continue;
-
- /* Set MPLL to 800MHz */
- set = SDIV(1) | PDIV(3) | MDIV(200) | PLL_ENABLE(1);
-
- clrsetbits_le32(&clk->mpll_con0, clr_pll_con0, set);
-
- while (!(readl(&clk->mpll_con0) & PLL_LOCKED_BIT))
- continue;
-
- /* Set CLKMUX_UART src to MPLL */
- clr = UART0_SEL(7) | UART1_SEL(7) | UART2_SEL(7) | UART3_SEL(7);
- set = UART0_SEL(3) | UART1_SEL(3) | UART2_SEL(3) | UART3_SEL(3);
-
- clrsetbits_le32(&clk->src_peric0, clr, set);
-
- /* Set SCLK_UART to 400 MHz (MPLL / 2) */
- clr = UART0_RATIO(15) | UART1_RATIO(15) | UART2_RATIO(15) |
- UART3_RATIO(15);
- set = UART0_RATIO(1) | UART1_RATIO(1) | UART2_RATIO(1) |
- UART3_RATIO(1);
-
- clrsetbits_le32(&clk->div_peric0, clr, set);
-
- while (readl(&clk->div_stat_peric0) & DIV_STAT_PERIC0_CHANGING)
- continue;
-
- /* Set CLKMUX_MMC src to MPLL */
- clr = MUX_MMC0_SEL(7) | MUX_MMC1_SEL(7) | MUX_MMC2_SEL(7);
- set = MUX_MMC0_SEL(3) | MUX_MMC1_SEL(3) | MUX_MMC2_SEL(3);
-
- clrsetbits_le32(&clk->src_fsys, clr, set);
-
- clr = MMC0_RATIO(0x3ff) | MMC1_RATIO(0x3ff) | MMC2_RATIO(0x3ff);
- set = MMC0_RATIO(0) | MMC1_RATIO(0) | MMC2_RATIO(0);
-
- clrsetbits_le32(&clk->div_fsys1, clr, set);
-
- /* Wait for divider ready status */
- while (readl(&clk->div_stat_fsys1) & DIV_STAT_FSYS1_CHANGING)
- continue;
-
- return 0;
-}
-
-int exynos_early_init_f(void)
-{
- return board_clock_init();
-}
-#endif
diff --git a/board/samsung/odroid-xu3/setup.h b/board/samsung/odroid-xu3/setup.h
deleted file mode 100644
index 143c189..0000000
--- a/board/samsung/odroid-xu3/setup.h
+++ /dev/null
@@ -1,95 +0,0 @@
-/*
- * (C) Copyright 2014 Samsung Electronics
- * Hyungwon Hwang <human.hw...@samsung.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __ODROID_XU3_SETUP__
-#define __ODROID_XU3_SETUP__
-
-#define SDIV(x) ((x) & 0x7)
-#define PDIV(x) (((x) & 0x3f) << 8)
-#define MDIV(x) (((x) & 0x3ff) << 16)
-#define FSEL(x) (((x) & 0x1) << 27)
-#define PLL_LOCKED_BIT (0x1 << 29)
-#define PLL_ENABLE(x) (((x) & 0x1) << 31)
-
-/* CLK_SRC_CPU */
-#define MUX_APLL_SEL(x) ((x) & 0x1)
-#define MUX_CORE_SEL(x) (((x) & 0x1) << 16)
-
-/* CLK_MUX_STAT_CPU */
-#define APLL_SEL(x) ((x) & 0x7)
-#define CORE_SEL(x) (((x) & 0x7) << 16)
-#define MUX_STAT_CPU_CHANGING(x) !(((x) & APLL_SEL(0)) || \
- (x) & APLL_SEL(1) || \
- (x) & CORE_SEL(0) || \
- (x) & CORE_SEL(1))
-
-/* CLK_DIV_CPU0 */
-#define ARM_RATIO(x) ((x) & 0x7)
-#define CPUD_RATIO(x) (((x) & 0x7) << 4)
-#define ATB_RATIO(x) (((x) & 0x7) << 16)
-#define PCLK_DBG_RATIO(x) (((x) & 0x7) << 20)
-#define APLL_RATIO(x) (((x) & 0x7) << 24)
-#define ARM2_RATIO(x) (((x) & 0x7) << 28)
-
-/* CLK_DIV_STAT_CPU0 */
-#define DIV_CPUD(x) (((x) & 0x1) << 4)
-#define DIV_ATB(x) (((x) & 0x1) << 16)
-#define DIV_PCLK_DBG(x) (((x) & 0x1) << 20)
-#define DIV_APLL(x) (((x) & 0x1) << 24)
-#define DIV_ARM2(x) (((x) & 0x1) << 28)
-
-#define DIV_STAT_CHANGING 0x1
-#define DIV_STAT_CPU0_CHANGING (DIV_CPUD(DIV_STAT_CHANGING) | \
- DIV_ATB(DIV_STAT_CHANGING) | \
- DIV_PCLK_DBG(DIV_STAT_CHANGING) | \
- DIV_APLL(DIV_STAT_CHANGING) | \
- DIV_ARM2(DIV_STAT_CHANGING))
-
-/* Set CLK_SRC_PERIC0 */
-#define UART0_SEL(x) (((x) & 0xf) << 4)
-#define UART1_SEL(x) (((x) & 0xf) << 8)
-#define UART2_SEL(x) (((x) & 0xf) << 12)
-#define UART3_SEL(x) (((x) & 0xf) << 16)
-
-/* Set CLK_DIV_PERIC0 */
-#define UART0_RATIO(x) (((x) & 0xf) << 8)
-#define UART1_RATIO(x) (((x) & 0xf) << 12)
-#define UART2_RATIO(x) (((x) & 0xf) << 16)
-#define UART3_RATIO(x) (((x) & 0xf) << 20)
-
-/* Set CLK_DIV_STAT_PERIC0 */
-#define DIV_UART0(x) ((x) & 0x1)
-#define DIV_UART1(x) (((x) & 0x1) << 4)
-#define DIV_UART2(x) (((x) & 0x1) << 8)
-#define DIV_UART3(x) (((x) & 0x1) << 12)
-#define DIV_UART4(x) (((x) & 0x1) << 16)
-
-#define DIV_STAT_PERIC0_CHANGING (DIV_UART4(DIV_STAT_CHANGING) | \
- DIV_UART3(DIV_STAT_CHANGING) | \
- DIV_UART2(DIV_STAT_CHANGING) | \
- DIV_UART1(DIV_STAT_CHANGING) | \
- DIV_UART0(DIV_STAT_CHANGING))
-
-/* CLK_SRC_FSYS */
-#define MUX_MMC0_SEL(x) (((x) & 0x7) << 8)
-#define MUX_MMC1_SEL(x) (((x) & 0x7) << 12)
-#define MUX_MMC2_SEL(x) (((x) & 0x7) << 16)
-
-/* CLK_DIV_FSYS1 */
-#define MMC0_RATIO(x) ((x) & 0x3ff)
-#define MMC1_RATIO(x) (((x) & 0x3ff) << 10)
-#define MMC2_RATIO(x) (((x) & 0x3ff) << 20)
-
-#define DIV_MMC0(x) (((x) & 1) << 20)
-#define DIV_MMC1(x) (((x) & 1) << 24)
-#define DIV_MMC2(x) (((x) & 1) << 28)
-
-#define DIV_STAT_FSYS1_CHANGING (DIV_MMC0(DIV_STAT_CHANGING) | \
- DIV_MMC1(DIV_STAT_CHANGING) | \
- DIV_MMC2(DIV_STAT_CHANGING))
-
-#endif
diff --git a/board/samsung/smdk5420/Kconfig b/board/samsung/smdk5420/Kconfig
index e7aafe5..ff28b1d 100644
--- a/board/samsung/smdk5420/Kconfig
+++ b/board/samsung/smdk5420/Kconfig
@@ -1,3 +1,16 @@
+if TARGET_ODROID_XU3
+
+config SYS_BOARD
+ default "smdk5420"
+
+config SYS_VENDOR
+ default "samsung"
+
+config SYS_CONFIG_NAME
+ default "odroid_xu3"
+
+endif
+
if TARGET_PEACH_PI
config SYS_BOARD
--
2.1.3
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