Thanks for your reviews. I did not know that the code from Simon Glass
is merged. I will remove this patch will be removed from the next
version.
Thanks.
Best regards,
Hyungwon Hwang
On Mon, 17 Nov 2014 10:51:21 +0100
Przemyslaw Marczak <p.marc...@samsung.com> wrote:
> Hello,
>
> Hyungwon, please check my last changes added to those files:
> - arch/arm/include/asm/arch-exynos/gpio.h
> (Exynos4x12 gpio enum and exynos4x12_gpio_data.)
> - arch/arm/include/asm/arch-exynos/cpu.h
> (Exynos4x12 gpio base sub parts)
>
> There was an issue with gaps between some of gpio banks, so I added
> sub parts definition and it was adequate to *pinctrl.dts and
> *pinctrl-uboot.dts description.
>
> First problem is, that device-tree description has some specified
> order
> - and this is the init order (and next real gpio numbering order).
>
> So if we have dts nodes like this:
> - pinctrl@13400000 { }
> - pinctrl@13410000 { }
> - pinctrl@14000000 { }
> - ...
> then it means, that gpio init should start from base 13400000 - which
> is "gpy70" tor the E5422... But there is one thing, which should be
> taken into account - "#include "exynos54xx-pinctrl-uboot.dtsi"",
> and actually the included file [...]uboot.dts, will define the gpio
> init order as:
> - pinctrl@14010000 - gpa00, gpa10, ..., gph00
> - pinctrl@13400000 - gpy70, gpx00, ..., gpx30 (gpx0->reg=<0xc00>)
> - pinctrl@13410000 - gpc00, ..., gpy60
> - pinctrl@14000000 - gpe00, ..., gpj40
> - pinctrl@03860000 - gpz00
>
> So, the above gpioXX bind order, should be equal to the enum
> exynos5420_gpio_pin { }. This is important, because if you type:
>
> ODROID-XU3 # gpio toggle gpy00
>
> then you will get the a result:
>
> gpio: pin gpy00 (gpio 160) value is 0
>
> Take a notice that gpy00 == gpio 160, but you defined it as 0 in your
> enum! So any call to the gpio inside the code, like this one:
>
> gpio_set_value(EXYNOS5420_GPIO_Y70, 0);
>
> like the pinmux do - will pass wrong gpio number to the function.
> And if you are lucky - some gpio numbers could work fine:)
>
> On 11/17/2014 08:45 AM, Simon Glass wrote:
> > Hi Hyungwon,
> >
> > On 14 November 2014 06:25, Hyungwon Hwang <human.hw...@samsung.com>
> > wrote:
> >> This patch fixes wrong GPIO information such as GPIO bank, table
> >> which is used to convert GPIO name to index, bank base address,
> >> and etc.
> >>
> >> Signed-off-by: Hyungwon Hwang <human.hw...@samsung.com>
> >> Tested-by: Lukasz Majewski <l.majew...@samsung.com>
> >> Acked-by: Lukasz Majewski <l.majew...@samsung.com>
> >> Cc: Minkyu Kang <mk7.k...@samsung.com>
> >> Cc: Lukasz Majewski <l.majew...@samsung.com>
> >> ---
> >> Changes for v4:
> >> - None
> >>
> >> Changes for v5:
> >> - None
> >>
> >> Changes for v6:
> >> - None
> >>
> >> Changes for v7:
> >> - None
> >>
> >> Changes for v8:
> >> - None
> >>
> >> arch/arm/include/asm/arch-exynos/cpu.h | 11 +-
> >> arch/arm/include/asm/arch-exynos/gpio.h | 232
> >> +++++++++++++++----------------- 2 files changed, 117
> >> insertions(+), 126 deletions(-)
> >>
> >> diff --git a/arch/arm/include/asm/arch-exynos/cpu.h
> >> b/arch/arm/include/asm/arch-exynos/cpu.h index 29674ad..48936de
> >> 100644 --- a/arch/arm/include/asm/arch-exynos/cpu.h
> >> +++ b/arch/arm/include/asm/arch-exynos/cpu.h
> >> @@ -148,7 +148,7 @@
> >>
> >> /* EXYNOS5420 */
> >> #define EXYNOS5420_AUDIOSS_BASE 0x03810000
> >> -#define EXYNOS5420_GPIO_PART6_BASE 0x03860000
> >> +#define EXYNOS5420_GPIO_PART5_BASE 0x03860000
> >> #define EXYNOS5420_PRO_ID 0x10000000
> >> #define EXYNOS5420_CLOCK_BASE 0x10010000
> >> #define EXYNOS5420_POWER_BASE 0x10040000
> >> @@ -170,11 +170,10 @@
> >> #define EXYNOS5420_I2S_BASE 0x12D60000
> >> #define EXYNOS5420_PWMTIMER_BASE 0x12DD0000
> >> #define EXYNOS5420_SPI_ISP_BASE 0x131A0000
> >> -#define EXYNOS5420_GPIO_PART2_BASE 0x13400000
> >> -#define EXYNOS5420_GPIO_PART3_BASE 0x13400C00
> >> -#define EXYNOS5420_GPIO_PART4_BASE 0x13410000
> >> -#define EXYNOS5420_GPIO_PART5_BASE 0x14000000
> >> -#define EXYNOS5420_GPIO_PART1_BASE 0x14010000
> >> +#define EXYNOS5420_GPIO_PART1_BASE 0x13400000
> >> +#define EXYNOS5420_GPIO_PART2_BASE 0x13410000
> >> +#define EXYNOS5420_GPIO_PART3_BASE 0x14000000
> >> +#define EXYNOS5420_GPIO_PART4_BASE 0x14010000
> >> #define EXYNOS5420_MIPI_DSIM_BASE 0x14500000
> >> #define EXYNOS5420_DP_BASE 0x145B0000
> >>
> >> diff --git a/arch/arm/include/asm/arch-exynos/gpio.h
> >> b/arch/arm/include/asm/arch-exynos/gpio.h index 9699954..aef897d
> >> 100644 --- a/arch/arm/include/asm/arch-exynos/gpio.h
> >> +++ b/arch/arm/include/asm/arch-exynos/gpio.h
> >> @@ -1042,83 +1042,7 @@ enum exynos5_gpio_pin {
> >> };
> >>
> >> enum exynos5420_gpio_pin {
> >> - /* GPIO_PART1_STARTS */
> >> - EXYNOS5420_GPIO_A00, /* 0 */
> >
> > Why does this order need to change? I think you might be trying to
> > remove the device tree work-around that we currently have. See
> > arch/arm/dts/exynos54xx-pinctrl-uboot.dtsi:
> >
> > /*
> > * Replicate the ordering of
> > arch/arm/include/asm/arch-exynos/gpio.h
> > * TODO(s...@chromium.org): This ordering ceases to matter
> > once GPIO
> > * numbers are not needed in U-Boot for exynos.
> > */
> > pinctrl@14010000 {
> > #address-cells = <1>;
> > #size-cells = <0>;
> > };
> > pinctrl@13400000 {
> > #address-cells = <1>;
> > #size-cells = <0>;
> > gpy7 {
> > };
> >
> > gpx0 {
> > reg = <0xc00>;
> > };
> > };
> >
> > Since you are changing things such that gpy7 comes first, I think
> > you need to update this file. But then don't you also need to
> > update all the numbering that we have in the various device tree
> > files? For example in exynos5420-peach-pit.dts:
> >
> > ec-interrupt = <&gpio 93 1>; /* GPX1_5 */
> >
> > The 93 will be wrong now I think - should it become 21?
> >
> > I do have a vague plan to implement proper device tree support for
> > GPIOs using driver model, so you could do:
> >
> > ec-interrupt = <&gpx1 5 GPIO_ACTIVE_LOW>;
> >
> > The gpx1 bit is already there. We need to bring over the dt-binding
> > header from Linux, and adjust the driver model uclass to understand
> > GPIO nodes better.
> >
> > But if you are not up for any of this, I wonder if you should just
> > change the ordering back?
> >
> > See also my comments below.
> >
>
> I agree with Simon, please don't change the pin order in this enum.
>
> >> - EXYNOS5420_GPIO_A01,
> >> - EXYNOS5420_GPIO_A02,
> >> - EXYNOS5420_GPIO_A03,
> >> - EXYNOS5420_GPIO_A04,
> >> - EXYNOS5420_GPIO_A05,
> >> - EXYNOS5420_GPIO_A06,
> >> - EXYNOS5420_GPIO_A07,
> >> - EXYNOS5420_GPIO_A10, /* 8 */
> >> - EXYNOS5420_GPIO_A11,
> >> - EXYNOS5420_GPIO_A12,
> >> - EXYNOS5420_GPIO_A13,
> >> - EXYNOS5420_GPIO_A14,
> >> - EXYNOS5420_GPIO_A15,
> >> - EXYNOS5420_GPIO_A16,
> >> - EXYNOS5420_GPIO_A17,
> >> - EXYNOS5420_GPIO_A20, /* 16 0x10 */
> >> - EXYNOS5420_GPIO_A21,
> >> - EXYNOS5420_GPIO_A22,
> >> - EXYNOS5420_GPIO_A23,
> >> - EXYNOS5420_GPIO_A24,
> >> - EXYNOS5420_GPIO_A25,
> >> - EXYNOS5420_GPIO_A26,
> >> - EXYNOS5420_GPIO_A27,
> >> - EXYNOS5420_GPIO_B00, /* 24 0x18 */
> >> - EXYNOS5420_GPIO_B01,
> >> - EXYNOS5420_GPIO_B02,
> >> - EXYNOS5420_GPIO_B03,
> >> - EXYNOS5420_GPIO_B04,
> >> - EXYNOS5420_GPIO_B05,
> >> - EXYNOS5420_GPIO_B06,
> >> - EXYNOS5420_GPIO_B07,
> >> - EXYNOS5420_GPIO_B10, /* 32 0x20 */
> >> - EXYNOS5420_GPIO_B11,
> >> - EXYNOS5420_GPIO_B12,
> >> - EXYNOS5420_GPIO_B13,
> >> - EXYNOS5420_GPIO_B14,
> >> - EXYNOS5420_GPIO_B15,
> >> - EXYNOS5420_GPIO_B16,
> >> - EXYNOS5420_GPIO_B17,
> >> - EXYNOS5420_GPIO_B20, /* 40 0x28 */
> >> - EXYNOS5420_GPIO_B21,
> >> - EXYNOS5420_GPIO_B22,
> >> - EXYNOS5420_GPIO_B23,
> >> - EXYNOS5420_GPIO_B24,
> >> - EXYNOS5420_GPIO_B25,
> >> - EXYNOS5420_GPIO_B26,
> >> - EXYNOS5420_GPIO_B27,
> >> - EXYNOS5420_GPIO_B30, /* 48 0x30 */
> >> - EXYNOS5420_GPIO_B31,
> >> - EXYNOS5420_GPIO_B32,
> >> - EXYNOS5420_GPIO_B33,
> >> - EXYNOS5420_GPIO_B34,
> >> - EXYNOS5420_GPIO_B35,
> >> - EXYNOS5420_GPIO_B36,
> >> - EXYNOS5420_GPIO_B37,
> >> - EXYNOS5420_GPIO_B40, /* 56 0x38 */
> >> - EXYNOS5420_GPIO_B41,
> >> - EXYNOS5420_GPIO_B42,
> >> - EXYNOS5420_GPIO_B43,
> >> - EXYNOS5420_GPIO_B44,
> >> - EXYNOS5420_GPIO_B45,
> >> - EXYNOS5420_GPIO_B46,
> >> - EXYNOS5420_GPIO_B47,
> >> - EXYNOS5420_GPIO_H00, /* 64 0x40 */
> >> - EXYNOS5420_GPIO_H01,
> >> - EXYNOS5420_GPIO_H02,
> >> - EXYNOS5420_GPIO_H03,
> >> - EXYNOS5420_GPIO_H04,
> >> - EXYNOS5420_GPIO_H05,
> >> - EXYNOS5420_GPIO_H06,
> >> - EXYNOS5420_GPIO_H07,
> >> -
> >> - /* GPIO PART 2 STARTS*/
> >> - EXYNOS5420_GPIO_MAX_PORT_PART_1,/* 72 0x48 */
> >> - EXYNOS5420_GPIO_Y70 = EXYNOS5420_GPIO_MAX_PORT_PART_1,
> >> + EXYNOS5420_GPIO_Y70,
> >> EXYNOS5420_GPIO_Y71,
> >> EXYNOS5420_GPIO_Y72,
> >> EXYNOS5420_GPIO_Y73,
> >> @@ -1126,10 +1050,7 @@ enum exynos5420_gpio_pin {
> >> EXYNOS5420_GPIO_Y75,
> >> EXYNOS5420_GPIO_Y76,
> >> EXYNOS5420_GPIO_Y77,
> >> -
> >> - /* GPIO PART 3 STARTS*/
> >> - EXYNOS5420_GPIO_MAX_PORT_PART_2,/* 80 0x50 */
> >> - EXYNOS5420_GPIO_X00 = EXYNOS5420_GPIO_MAX_PORT_PART_2,
> >> + EXYNOS5420_GPIO_X00,
> >> EXYNOS5420_GPIO_X01,
> >> EXYNOS5420_GPIO_X02,
> >> EXYNOS5420_GPIO_X03,
> >> @@ -1137,7 +1058,7 @@ enum exynos5420_gpio_pin {
> >> EXYNOS5420_GPIO_X05,
> >> EXYNOS5420_GPIO_X06,
> >> EXYNOS5420_GPIO_X07,
> >> - EXYNOS5420_GPIO_X10, /* 88 0x58 */
> >> + EXYNOS5420_GPIO_X10,
> >> EXYNOS5420_GPIO_X11,
> >> EXYNOS5420_GPIO_X12,
> >> EXYNOS5420_GPIO_X13,
> >> @@ -1145,7 +1066,7 @@ enum exynos5420_gpio_pin {
> >> EXYNOS5420_GPIO_X15,
> >> EXYNOS5420_GPIO_X16,
> >> EXYNOS5420_GPIO_X17,
> >> - EXYNOS5420_GPIO_X20, /* 96 0x60 */
> >> + EXYNOS5420_GPIO_X20,
> >> EXYNOS5420_GPIO_X21,
> >> EXYNOS5420_GPIO_X22,
> >> EXYNOS5420_GPIO_X23,
> >> @@ -1153,7 +1074,7 @@ enum exynos5420_gpio_pin {
> >> EXYNOS5420_GPIO_X25,
> >> EXYNOS5420_GPIO_X26,
> >> EXYNOS5420_GPIO_X27,
> >> - EXYNOS5420_GPIO_X30, /* 104 0x68 */
> >> + EXYNOS5420_GPIO_X30,
> >> EXYNOS5420_GPIO_X31,
> >> EXYNOS5420_GPIO_X32,
> >> EXYNOS5420_GPIO_X33,
> >> @@ -1162,9 +1083,8 @@ enum exynos5420_gpio_pin {
> >> EXYNOS5420_GPIO_X36,
> >> EXYNOS5420_GPIO_X37,
> >>
> >> - /* GPIO PART 4 STARTS*/
> >> - EXYNOS5420_GPIO_MAX_PORT_PART_3,/* 112 0x70 */
> >> - EXYNOS5420_GPIO_C00 = EXYNOS5420_GPIO_MAX_PORT_PART_3,
> >> + EXYNOS5420_GPIO_MAX_PORT_PART_1,
> >> + EXYNOS5420_GPIO_C00 = EXYNOS5420_GPIO_MAX_PORT_PART_1,
> >> EXYNOS5420_GPIO_C01,
> >> EXYNOS5420_GPIO_C02,
> >> EXYNOS5420_GPIO_C03,
> >> @@ -1172,7 +1092,7 @@ enum exynos5420_gpio_pin {
> >> EXYNOS5420_GPIO_C05,
> >> EXYNOS5420_GPIO_C06,
> >> EXYNOS5420_GPIO_C07,
> >> - EXYNOS5420_GPIO_C10, /* 120 0x78 */
> >> + EXYNOS5420_GPIO_C10,
> >> EXYNOS5420_GPIO_C11,
> >> EXYNOS5420_GPIO_C12,
> >> EXYNOS5420_GPIO_C13,
> >> @@ -1180,7 +1100,7 @@ enum exynos5420_gpio_pin {
> >> EXYNOS5420_GPIO_C15,
> >> EXYNOS5420_GPIO_C16,
> >> EXYNOS5420_GPIO_C17,
> >> - EXYNOS5420_GPIO_C20, /* 128 0x80 */
> >> + EXYNOS5420_GPIO_C20,
> >> EXYNOS5420_GPIO_C21,
> >> EXYNOS5420_GPIO_C22,
> >> EXYNOS5420_GPIO_C23,
> >> @@ -1188,7 +1108,7 @@ enum exynos5420_gpio_pin {
> >> EXYNOS5420_GPIO_C25,
> >> EXYNOS5420_GPIO_C26,
> >> EXYNOS5420_GPIO_C27,
> >> - EXYNOS5420_GPIO_C30, /* 136 0x88 */
> >> + EXYNOS5420_GPIO_C30,
> >> EXYNOS5420_GPIO_C31,
> >> EXYNOS5420_GPIO_C32,
> >> EXYNOS5420_GPIO_C33,
> >> @@ -1196,7 +1116,7 @@ enum exynos5420_gpio_pin {
> >> EXYNOS5420_GPIO_C35,
> >> EXYNOS5420_GPIO_C36,
> >> EXYNOS5420_GPIO_C37,
> >> - EXYNOS5420_GPIO_C40, /* 144 0x90 */
> >> + EXYNOS5420_GPIO_C40,
> >> EXYNOS5420_GPIO_C41,
> >> EXYNOS5420_GPIO_C42,
> >> EXYNOS5420_GPIO_C43,
> >> @@ -1204,7 +1124,7 @@ enum exynos5420_gpio_pin {
> >> EXYNOS5420_GPIO_C45,
> >> EXYNOS5420_GPIO_C46,
> >> EXYNOS5420_GPIO_C47,
> >> - EXYNOS5420_GPIO_D10, /* 152 0x98 */
> >> + EXYNOS5420_GPIO_D10,
> >> EXYNOS5420_GPIO_D11,
> >> EXYNOS5420_GPIO_D12,
> >> EXYNOS5420_GPIO_D13,
> >> @@ -1212,7 +1132,7 @@ enum exynos5420_gpio_pin {
> >> EXYNOS5420_GPIO_D15,
> >> EXYNOS5420_GPIO_D16,
> >> EXYNOS5420_GPIO_D17,
> >> - EXYNOS5420_GPIO_Y00, /* 160 0xa0 */
> >> + EXYNOS5420_GPIO_Y00,
> >> EXYNOS5420_GPIO_Y01,
> >> EXYNOS5420_GPIO_Y02,
> >> EXYNOS5420_GPIO_Y03,
> >> @@ -1220,7 +1140,7 @@ enum exynos5420_gpio_pin {
> >> EXYNOS5420_GPIO_Y05,
> >> EXYNOS5420_GPIO_Y06,
> >> EXYNOS5420_GPIO_Y07,
> >> - EXYNOS5420_GPIO_Y10, /* 168 0xa8 */
> >> + EXYNOS5420_GPIO_Y10,
> >> EXYNOS5420_GPIO_Y11,
> >> EXYNOS5420_GPIO_Y12,
> >> EXYNOS5420_GPIO_Y13,
> >> @@ -1228,7 +1148,7 @@ enum exynos5420_gpio_pin {
> >> EXYNOS5420_GPIO_Y15,
> >> EXYNOS5420_GPIO_Y16,
> >> EXYNOS5420_GPIO_Y17,
> >> - EXYNOS5420_GPIO_Y20, /* 176 0xb0 */
> >> + EXYNOS5420_GPIO_Y20,
> >> EXYNOS5420_GPIO_Y21,
> >> EXYNOS5420_GPIO_Y22,
> >> EXYNOS5420_GPIO_Y23,
> >> @@ -1236,7 +1156,7 @@ enum exynos5420_gpio_pin {
> >> EXYNOS5420_GPIO_Y25,
> >> EXYNOS5420_GPIO_Y26,
> >> EXYNOS5420_GPIO_Y27,
> >> - EXYNOS5420_GPIO_Y30, /* 184 0xb8 */
> >> + EXYNOS5420_GPIO_Y30,
> >> EXYNOS5420_GPIO_Y31,
> >> EXYNOS5420_GPIO_Y32,
> >> EXYNOS5420_GPIO_Y33,
> >> @@ -1244,7 +1164,7 @@ enum exynos5420_gpio_pin {
> >> EXYNOS5420_GPIO_Y35,
> >> EXYNOS5420_GPIO_Y36,
> >> EXYNOS5420_GPIO_Y37,
> >> - EXYNOS5420_GPIO_Y40, /* 192 0xc0 */
> >> + EXYNOS5420_GPIO_Y40,
> >> EXYNOS5420_GPIO_Y41,
> >> EXYNOS5420_GPIO_Y42,
> >> EXYNOS5420_GPIO_Y43,
> >> @@ -1252,7 +1172,7 @@ enum exynos5420_gpio_pin {
> >> EXYNOS5420_GPIO_Y45,
> >> EXYNOS5420_GPIO_Y46,
> >> EXYNOS5420_GPIO_Y47,
> >> - EXYNOS5420_GPIO_Y50, /* 200 0xc8 */
> >> + EXYNOS5420_GPIO_Y50,
> >> EXYNOS5420_GPIO_Y51,
> >> EXYNOS5420_GPIO_Y52,
> >> EXYNOS5420_GPIO_Y53,
> >> @@ -1260,7 +1180,7 @@ enum exynos5420_gpio_pin {
> >> EXYNOS5420_GPIO_Y55,
> >> EXYNOS5420_GPIO_Y56,
> >> EXYNOS5420_GPIO_Y57,
> >> - EXYNOS5420_GPIO_Y60, /* 208 0xd0 */
> >> + EXYNOS5420_GPIO_Y60,
> >> EXYNOS5420_GPIO_Y61,
> >> EXYNOS5420_GPIO_Y62,
> >> EXYNOS5420_GPIO_Y63,
> >> @@ -1269,9 +1189,8 @@ enum exynos5420_gpio_pin {
> >> EXYNOS5420_GPIO_Y66,
> >> EXYNOS5420_GPIO_Y67,
> >>
> >> - /* GPIO_PART5_STARTS */
> >> - EXYNOS5420_GPIO_MAX_PORT_PART_4,/* 216 0xd8 */
> >> - EXYNOS5420_GPIO_E00 = EXYNOS5420_GPIO_MAX_PORT_PART_4,
> >> + EXYNOS5420_GPIO_MAX_PORT_PART_2,
> >> + EXYNOS5420_GPIO_E00 = EXYNOS5420_GPIO_MAX_PORT_PART_2,
> >> EXYNOS5420_GPIO_E01,
> >> EXYNOS5420_GPIO_E02,
> >> EXYNOS5420_GPIO_E03,
> >> @@ -1279,7 +1198,7 @@ enum exynos5420_gpio_pin {
> >> EXYNOS5420_GPIO_E05,
> >> EXYNOS5420_GPIO_E06,
> >> EXYNOS5420_GPIO_E07,
> >> - EXYNOS5420_GPIO_E10, /* 224 0xe0 */
> >> + EXYNOS5420_GPIO_E10,
> >> EXYNOS5420_GPIO_E11,
> >> EXYNOS5420_GPIO_E12,
> >> EXYNOS5420_GPIO_E13,
> >> @@ -1287,7 +1206,7 @@ enum exynos5420_gpio_pin {
> >> EXYNOS5420_GPIO_E15,
> >> EXYNOS5420_GPIO_E16,
> >> EXYNOS5420_GPIO_E17,
> >> - EXYNOS5420_GPIO_F00, /* 232 0xe8 */
> >> + EXYNOS5420_GPIO_F00,
> >> EXYNOS5420_GPIO_F01,
> >> EXYNOS5420_GPIO_F02,
> >> EXYNOS5420_GPIO_F03,
> >> @@ -1295,7 +1214,7 @@ enum exynos5420_gpio_pin {
> >> EXYNOS5420_GPIO_F05,
> >> EXYNOS5420_GPIO_F06,
> >> EXYNOS5420_GPIO_F07,
> >> - EXYNOS5420_GPIO_F10, /* 240 0xf0 */
> >> + EXYNOS5420_GPIO_F10,
> >> EXYNOS5420_GPIO_F11,
> >> EXYNOS5420_GPIO_F12,
> >> EXYNOS5420_GPIO_F13,
> >> @@ -1303,7 +1222,7 @@ enum exynos5420_gpio_pin {
> >> EXYNOS5420_GPIO_F15,
> >> EXYNOS5420_GPIO_F16,
> >> EXYNOS5420_GPIO_F17,
> >> - EXYNOS5420_GPIO_G00, /* 248 0xf8 */
> >> + EXYNOS5420_GPIO_G00,
> >> EXYNOS5420_GPIO_G01,
> >> EXYNOS5420_GPIO_G02,
> >> EXYNOS5420_GPIO_G03,
> >> @@ -1311,7 +1230,7 @@ enum exynos5420_gpio_pin {
> >> EXYNOS5420_GPIO_G05,
> >> EXYNOS5420_GPIO_G06,
> >> EXYNOS5420_GPIO_G07,
> >> - EXYNOS5420_GPIO_G10, /* 256 0x100 */
> >> + EXYNOS5420_GPIO_G10,
> >> EXYNOS5420_GPIO_G11,
> >> EXYNOS5420_GPIO_G12,
> >> EXYNOS5420_GPIO_G13,
> >> @@ -1319,7 +1238,7 @@ enum exynos5420_gpio_pin {
> >> EXYNOS5420_GPIO_G15,
> >> EXYNOS5420_GPIO_G16,
> >> EXYNOS5420_GPIO_G17,
> >> - EXYNOS5420_GPIO_G20, /* 264 0x108 */
> >> + EXYNOS5420_GPIO_G20,
> >> EXYNOS5420_GPIO_G21,
> >> EXYNOS5420_GPIO_G22,
> >> EXYNOS5420_GPIO_G23,
> >> @@ -1327,7 +1246,7 @@ enum exynos5420_gpio_pin {
> >> EXYNOS5420_GPIO_G25,
> >> EXYNOS5420_GPIO_G26,
> >> EXYNOS5420_GPIO_G27,
> >> - EXYNOS5420_GPIO_J40, /* 272 0x110 */
> >> + EXYNOS5420_GPIO_J40,
> >> EXYNOS5420_GPIO_J41,
> >> EXYNOS5420_GPIO_J42,
> >> EXYNOS5420_GPIO_J43,
> >> @@ -1336,15 +1255,89 @@ enum exynos5420_gpio_pin {
> >> EXYNOS5420_GPIO_J46,
> >> EXYNOS5420_GPIO_J47,
> >>
> >> - /* GPIO_PART6_STARTS */
> >> - EXYNOS5420_GPIO_MAX_PORT_PART_5,/* 280 0x118 */
> >> - EXYNOS5420_GPIO_Z0 = EXYNOS5420_GPIO_MAX_PORT_PART_5,
> >> + EXYNOS5420_GPIO_MAX_PORT_PART_3,
> >> + EXYNOS5420_GPIO_A00 = EXYNOS5420_GPIO_MAX_PORT_PART_3,
> >> + EXYNOS5420_GPIO_A01,
> >> + EXYNOS5420_GPIO_A02,
> >> + EXYNOS5420_GPIO_A03,
> >> + EXYNOS5420_GPIO_A04,
> >> + EXYNOS5420_GPIO_A05,
> >> + EXYNOS5420_GPIO_A06,
> >> + EXYNOS5420_GPIO_A07,
> >> + EXYNOS5420_GPIO_A10,
> >> + EXYNOS5420_GPIO_A11,
> >> + EXYNOS5420_GPIO_A12,
> >> + EXYNOS5420_GPIO_A13,
> >> + EXYNOS5420_GPIO_A14,
> >> + EXYNOS5420_GPIO_A15,
> >> + EXYNOS5420_GPIO_A16,
> >> + EXYNOS5420_GPIO_A17,
> >> + EXYNOS5420_GPIO_A20,
> >> + EXYNOS5420_GPIO_A21,
> >> + EXYNOS5420_GPIO_A22,
> >> + EXYNOS5420_GPIO_A23,
> >> + EXYNOS5420_GPIO_A24,
> >> + EXYNOS5420_GPIO_A25,
> >> + EXYNOS5420_GPIO_A26,
> >> + EXYNOS5420_GPIO_A27,
> >> + EXYNOS5420_GPIO_B00,
> >> + EXYNOS5420_GPIO_B01,
> >> + EXYNOS5420_GPIO_B02,
> >> + EXYNOS5420_GPIO_B03,
> >> + EXYNOS5420_GPIO_B04,
> >> + EXYNOS5420_GPIO_B05,
> >> + EXYNOS5420_GPIO_B06,
> >> + EXYNOS5420_GPIO_B07,
> >> + EXYNOS5420_GPIO_B10,
> >> + EXYNOS5420_GPIO_B11,
> >> + EXYNOS5420_GPIO_B12,
> >> + EXYNOS5420_GPIO_B13,
> >> + EXYNOS5420_GPIO_B14,
> >> + EXYNOS5420_GPIO_B15,
> >> + EXYNOS5420_GPIO_B16,
> >> + EXYNOS5420_GPIO_B17,
> >> + EXYNOS5420_GPIO_B20,
> >> + EXYNOS5420_GPIO_B21,
> >> + EXYNOS5420_GPIO_B22,
> >> + EXYNOS5420_GPIO_B23,
> >> + EXYNOS5420_GPIO_B24,
> >> + EXYNOS5420_GPIO_B25,
> >> + EXYNOS5420_GPIO_B26,
> >> + EXYNOS5420_GPIO_B27,
> >> + EXYNOS5420_GPIO_B30,
> >> + EXYNOS5420_GPIO_B31,
> >> + EXYNOS5420_GPIO_B32,
> >> + EXYNOS5420_GPIO_B33,
> >> + EXYNOS5420_GPIO_B34,
> >> + EXYNOS5420_GPIO_B35,
> >> + EXYNOS5420_GPIO_B36,
> >> + EXYNOS5420_GPIO_B37,
> >> + EXYNOS5420_GPIO_B40,
> >> + EXYNOS5420_GPIO_B41,
> >> + EXYNOS5420_GPIO_B42,
> >> + EXYNOS5420_GPIO_B43,
> >> + EXYNOS5420_GPIO_B44,
> >> + EXYNOS5420_GPIO_B45,
> >> + EXYNOS5420_GPIO_B46,
> >> + EXYNOS5420_GPIO_B47,
> >> + EXYNOS5420_GPIO_H00,
> >> + EXYNOS5420_GPIO_H01,
> >> + EXYNOS5420_GPIO_H02,
> >> + EXYNOS5420_GPIO_H03,
> >> + EXYNOS5420_GPIO_H04,
> >> + EXYNOS5420_GPIO_H05,
> >> + EXYNOS5420_GPIO_H06,
> >> + EXYNOS5420_GPIO_H07,
> >> +
> >> + EXYNOS5420_GPIO_MAX_PORT_PART_4,
> >> + EXYNOS5420_GPIO_Z0 = EXYNOS5420_GPIO_MAX_PORT_PART_4,
> >> EXYNOS5420_GPIO_Z1,
> >> EXYNOS5420_GPIO_Z2,
> >> EXYNOS5420_GPIO_Z3,
> >> EXYNOS5420_GPIO_Z4,
> >> EXYNOS5420_GPIO_Z5,
> >> EXYNOS5420_GPIO_Z6,
> >> +
> >> EXYNOS5420_GPIO_MAX_PORT
> >> };
> >>
> >> @@ -1385,14 +1378,13 @@ static struct gpio_info
> >> exynos5_gpio_data[EXYNOS5_GPIO_NUM_PARTS] =
> >> { { EXYNOS5_GPIO_PART8_BASE, EXYNOS5_GPIO_MAX_PORT }, };
> >>
> >> -#define EXYNOS5420_GPIO_NUM_PARTS 6
> >> +#define EXYNOS5420_GPIO_NUM_PARTS 5
>
> And this code should be updated with additional parts like Exynos4x12
> has. See the gap between gpy7 and gpx0. But this was actually for
> non-dm gpio calls - probably in the future those definitions could be
> removed.
>
> >> static struct gpio_info
> >> exynos5420_gpio_data[EXYNOS5420_GPIO_NUM_PARTS] =
> >> { { EXYNOS5420_GPIO_PART1_BASE, EXYNOS5420_GPIO_MAX_PORT_PART_1 },
> >> { EXYNOS5420_GPIO_PART2_BASE, EXYNOS5420_GPIO_MAX_PORT_PART_2 },
> >> { EXYNOS5420_GPIO_PART3_BASE, EXYNOS5420_GPIO_MAX_PORT_PART_3 },
> >> { EXYNOS5420_GPIO_PART4_BASE, EXYNOS5420_GPIO_MAX_PORT_PART_4 },
> >> - { EXYNOS5420_GPIO_PART5_BASE,
> >> EXYNOS5420_GPIO_MAX_PORT_PART_5 },
> >> - { EXYNOS5420_GPIO_PART6_BASE, EXYNOS5420_GPIO_MAX_PORT },
> >> + { EXYNOS5420_GPIO_PART5_BASE, EXYNOS5420_GPIO_MAX_PORT },
> >> };
> >>
> >> static inline struct gpio_info *get_gpio_data(void)
> >> @@ -1505,17 +1497,17 @@ static const struct gpio_name_num_table
> >> exynos5_gpio_table[] = { };
> >>
> >> static const struct gpio_name_num_table exynos5420_gpio_table[]
> >> = {
> >> - GPIO_ENTRY('a', EXYNOS5420_GPIO_A00, EXYNOS5420_GPIO_B00,
> >> 0),
> >> - GPIO_ENTRY('b', EXYNOS5420_GPIO_B00, EXYNOS5420_GPIO_H00,
> >> 0),
> >> - GPIO_ENTRY('h', EXYNOS5420_GPIO_H00, EXYNOS5420_GPIO_Y70,
> >> 0), GPIO_ENTRY('x', EXYNOS5420_GPIO_X00, EXYNOS5420_GPIO_C00, 0),
> >> GPIO_ENTRY('c', EXYNOS5420_GPIO_C00, EXYNOS5420_GPIO_D10,
> >> 0),
> >> - GPIO_ENTRY('d', EXYNOS5420_GPIO_D10, EXYNOS5420_GPIO_Y00,
> >> 010),
> >> + GPIO_ENTRY('d', EXYNOS5420_GPIO_D10, EXYNOS5420_GPIO_Y00,
> >> 0), GPIO_ENTRY('y', EXYNOS5420_GPIO_Y00, EXYNOS5420_GPIO_E00, 0),
> >> GPIO_ENTRY('e', EXYNOS5420_GPIO_E00, EXYNOS5420_GPIO_F00,
> >> 0), GPIO_ENTRY('f', EXYNOS5420_GPIO_F00, EXYNOS5420_GPIO_G00, 0),
> >> GPIO_ENTRY('g', EXYNOS5420_GPIO_G00, EXYNOS5420_GPIO_J40,
> >> 0),
> >> - GPIO_ENTRY('j', EXYNOS5420_GPIO_J40, EXYNOS5420_GPIO_Z0,
> >> 040),
> >> + GPIO_ENTRY('j', EXYNOS5420_GPIO_J40, EXYNOS5420_GPIO_A00,
> >> 0),
> >> + GPIO_ENTRY('a', EXYNOS5420_GPIO_A00, EXYNOS5420_GPIO_B00,
> >> 0),
> >> + GPIO_ENTRY('b', EXYNOS5420_GPIO_B00, EXYNOS5420_GPIO_H00,
> >> 0),
> >> + GPIO_ENTRY('h', EXYNOS5420_GPIO_H00, EXYNOS5420_GPIO_Z0,
> >> 0), GPIO_ENTRY('z', EXYNOS5420_GPIO_Z0, EXYNOS5420_GPIO_MAX_PORT,
> >> 0), { 0 }
> >> };
> >
> > I don't believe these arrays are used anymore. You should be able to
> > create a patch to delete them.
> >
> > Regards,
> > Simon
> >
>
> Best regards,
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