Hi Peng,
On 11/1/2014 10:19 AM, Peng Fan wrote:
> Add a new function mxc_iomux_set_gpr_register to
> set the iomux gpr register.
>
> 32-bit general purpose registers according to SoC
> requirements for any usage.
>
> Signed-off-by: Peng Fan <peng....@freescale.com>
> Signed-off-by: Ye.Li <b37...@freescale.com>
> Signed-off-by: Nitin Garg <nitin.g...@freescale.com>
> ---
> arch/arm/imx-common/iomux-v3.c | 25 +++++++++++++++++++++++++
> 1 file changed, 25 insertions(+)
>
> diff --git a/arch/arm/imx-common/iomux-v3.c b/arch/arm/imx-common/iomux-v3.c
> index 22cd11a..b27aab8 100644
> --- a/arch/arm/imx-common/iomux-v3.c
> +++ b/arch/arm/imx-common/iomux-v3.c
> @@ -77,3 +77,28 @@ void imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t const
> *pad_list,
> p += stride;
> }
> }
> +
> +/*
> + * Configure the IOMUX General Purpose Registers.
> + *
> + * @group, which gpr register to configure.
> + * @start_bit, the first bit to set
> + * @num_bits, how many bits to set
> + * @value, the value will be set to [start_bits...start_bits+num_bits-1]
> + */
> +void mxc_iomux_set_gpr_register(int group, int start_bit, int num_bits,
> + int value)
> +{
> + int i = 0;
> + u32 reg;
> +
> + reg = readl(base + group * 4);
> + while (num_bits) {
> + reg &= ~(1 << (start_bit + i));
> + i++;
> + num_bits--;
> + }
> +
> + reg |= (value << start_bit);
> + writel(reg, base + group * 4);
> +}
This function is already in my previous patch
(http://patchwork.ozlabs.org/patch/405013/). The function name is changed to
imx_iomux_set_gpr_register.
Best regards,
Ye Li
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