After remove the offsets in Exynos4/4x12 gpio enums, an addidional gpio base
addresses are required.

Signed-off-by: Przemyslaw Marczak <p.marc...@samsung.com>
---
 arch/arm/include/asm/arch-exynos/cpu.h | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/arch/arm/include/asm/arch-exynos/cpu.h 
b/arch/arm/include/asm/arch-exynos/cpu.h
index ba71714..78aceef 100644
--- a/arch/arm/include/asm/arch-exynos/cpu.h
+++ b/arch/arm/include/asm/arch-exynos/cpu.h
@@ -29,6 +29,8 @@
 #define EXYNOS4_MIU_BASE               0x10600000
 #define EXYNOS4_ACE_SFR_BASE           0x10830000
 #define EXYNOS4_GPIO_PART2_BASE                0x11000000
+#define EXYNOS4_GPIO_PART2_0           0x11000000 /* GPJ0 */
+#define EXYNOS4_GPIO_PART2_1           0x11000c00 /* GPX0 */
 #define EXYNOS4_GPIO_PART1_BASE                0x11400000
 #define EXYNOS4_FIMD_BASE              0x11C00000
 #define EXYNOS4_MIPI_DSIM_BASE         0x11C80000
@@ -70,7 +72,14 @@
 #define EXYNOS4X12_GPIO_PART4_BASE     0x106E0000
 #define EXYNOS4X12_ACE_SFR_BASE                0x10830000
 #define EXYNOS4X12_GPIO_PART2_BASE     0x11000000
+#define EXYNOS4X12_GPIO_PART2_0                0x11000000
+#define EXYNOS4X12_GPIO_PART2_1                0x11000040 /* GPK0 */
+#define EXYNOS4X12_GPIO_PART2_2                0x11000260 /* GPM0 */
+#define EXYNOS4X12_GPIO_PART2_3                0x11000c00 /* GPX0 */
 #define EXYNOS4X12_GPIO_PART1_BASE     0x11400000
+#define EXYNOS4X12_GPIO_PART1_0                0x11400000 /* GPA0 */
+#define EXYNOS4X12_GPIO_PART1_1                0x11400180 /* GPF0 */
+#define EXYNOS4X12_GPIO_PART1_2                0x11400240 /* GPJ0 */
 #define EXYNOS4X12_FIMD_BASE           0x11C00000
 #define EXYNOS4X12_MIPI_DSIM_BASE      0x11C80000
 #define EXYNOS4X12_USBOTG_BASE         0x12480000
-- 
1.9.1

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