Add more information so that U-Boot can find the address of the serial port.
Also fix the reg-shift value.

Signed-off-by: Simon Glass <s...@chromium.org>
---

 arch/x86/dts/coreboot.dtsi |  5 +++--
 arch/x86/dts/link.dts      | 18 +++++++++++++++++-
 2 files changed, 20 insertions(+), 3 deletions(-)

diff --git a/arch/x86/dts/coreboot.dtsi b/arch/x86/dts/coreboot.dtsi
index 4862a59..c989152 100644
--- a/arch/x86/dts/coreboot.dtsi
+++ b/arch/x86/dts/coreboot.dtsi
@@ -6,8 +6,9 @@
        };
 
        serial {
-               compatible = "ns16550";
-               reg-shift = <1>;
+               compatible = "coreboot-uart";
+               reg = <0x3f8 0x10>;
+               reg-shift = <0>;
                io-mapped = <1>;
                multiplier = <1>;
                baudrate = <115200>;
diff --git a/arch/x86/dts/link.dts b/arch/x86/dts/link.dts
index 67ce52a..f2fcb39 100644
--- a/arch/x86/dts/link.dts
+++ b/arch/x86/dts/link.dts
@@ -12,7 +12,23 @@
               silent_console = <0>;
        };
 
-       gpio: gpio {};
+       gpioa {
+               compatible = "intel,ich6-gpio";
+               reg = <0 0x10>;
+               bank-name = "A";
+       };
+
+       gpiob {
+               compatible = "intel,ich6-gpio";
+               reg = <0x30 0x10>;
+               bank-name = "B";
+       };
+
+       gpioc {
+               compatible = "intel,ich6-gpio";
+               reg = <0x40 0x10>;
+               bank-name = "C";
+       };
 
        serial {
                reg = <0x3f8 8>;
-- 
2.1.0.rc2.206.gedb03e5

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