On 09/09/2014 04:17, Ye.Li wrote: > Checking the pre_periph_clk_sel and pre_periph2_clk of CCM CBCMR > register, if the PLL2 PFD0 or PLL2 PFD2 is used for the clock source, > do not reset this PFD to avoid system hang. Customers may set this > in DDR script or use BT_FREQ to select low freq boot. > > Signed-off-by: Ye.Li <b37...@freescale.com> > ---
Applied to u-boot-imx, thanks ! Best regards, Stefano Babic -- ===================================================================== DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de ===================================================================== _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
