Hardware accelerated support for SHA-1 and SHA-256 has been added.
Hash command enabled along with hardware accelerated support for
SHA-1 and SHA-256 for platforms which have CAAM block.
Signed-off-by: Ruchika Gupta <ruchika.gu...@freescale.com>
CC: York Sun <york...@freescale.com>
---
arch/arm/include/asm/arch-ls102xa/config.h | 10 ++++++++++
board/freescale/ls1021aqds/ls1021aqds.c | 10 ++++++++++
board/freescale/ls1021atwr/ls1021atwr.c | 9 +++++++++
include/configs/ls1021aqds.h | 6 ++++++
include/configs/ls1021atwr.h | 6 ++++++
5 files changed, 41 insertions(+)
diff --git a/arch/arm/include/asm/arch-ls102xa/config.h
b/arch/arm/include/asm/arch-ls102xa/config.h
index ed78c33..b6cb857 100644
--- a/arch/arm/include/asm/arch-ls102xa/config.h
+++ b/arch/arm/include/asm/arch-ls102xa/config.h
@@ -20,6 +20,8 @@
#define CONFIG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x00560000)
#define CONFIG_SYS_FSL_SCFG_ADDR (CONFIG_SYS_IMMR + 0x00570000)
#define CONFIG_SYS_FSL_SERDES_ADDR (CONFIG_SYS_IMMR + 0x00ea0000)
+#define CONFIG_SYS_FSL_SEC_ADDR (CONFIG_SYS_IMMR +
0x700000)
+#define CONFIG_SYS_FSL_JR0_ADDR (CONFIG_SYS_IMMR +
0x710000)
#define CONFIG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00ee0000)
#define CONFIG_SYS_FSL_LS1_CLK_ADDR (CONFIG_SYS_IMMR + 0x00ee1000)
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR +
0x011c0500)
@@ -71,8 +73,16 @@
#define CONFIG_MAX_CPUS 2
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
#define CONFIG_NUM_DDR_CONTROLLERS 1
+#define CONFIG_SYS_FSL_SEC_OFFSET 0x00700000
+#define CONFIG_SYS_FSL_SEC_COMPAT 5
#else
#error SoC not defined
#endif
+#define CONFIG_SYS_FSL_SEC_LE
+
+#if CONFIG_SYS_FSL_SEC_COMPAT >= 4
+#define CONFIG_FSL_CAAM
+#endif
+
#endif /* _ASM_ARMV7_LS102XA_CONFIG_ */
diff --git a/board/freescale/ls1021aqds/ls1021aqds.c
b/board/freescale/ls1021aqds/ls1021aqds.c
index 12e83f7..d6278b9 100644
--- a/board/freescale/ls1021aqds/ls1021aqds.c
+++ b/board/freescale/ls1021aqds/ls1021aqds.c
@@ -13,6 +13,7 @@
#include <mmc.h>
#include <fsl_esdhc.h>
#include <fsl_ifc.h>
+#include <fsl_sec.h>
#include "../common/qixis.h"
#include "ls1021aqds_qixis.h"
@@ -213,6 +214,15 @@ int config_serdes_mux(void)
return 0;
}
+#if defined(CONFIG_MISC_INIT_R)
+int misc_init_r(void)
+{
+ if (sec_init() < 0)
+ return -1;
+ return 0;
+}
+#endif
+
int board_init(void)
{
struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
diff --git a/board/freescale/ls1021atwr/ls1021atwr.c
b/board/freescale/ls1021atwr/ls1021atwr.c
index b522ff2..80903f6 100644
--- a/board/freescale/ls1021atwr/ls1021atwr.c
+++ b/board/freescale/ls1021atwr/ls1021atwr.c
@@ -280,6 +280,15 @@ int board_init(void)
return 0;
}
+#if defined(CONFIG_MISC_INIT_R)
+int misc_init_r(void)
+{
+ if (sec_init() < 0)
+ return -1;
+ return 0;
+}
+#endif
+
void ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h
index 657e3b6..df2fc09 100644
--- a/include/configs/ls1021aqds.h
+++ b/include/configs/ls1021aqds.h
@@ -386,4 +386,10 @@ unsigned long get_board_ddr_clk(void);
#define CONFIG_OF_BOARD_SETUP
#define CONFIG_CMD_BOOTZ
+#define CONFIG_MISC_INIT_R
+
+/* Hash command with SHA acceleration supported in hardware */
+#define CONFIG_CMD_HASH
+#define CONFIG_SHA_HW_ACCEL
+
#endif
diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h
index 45b2272..7199c92 100644
--- a/include/configs/ls1021atwr.h
+++ b/include/configs/ls1021atwr.h
@@ -288,4 +288,10 @@
#define CONFIG_OF_BOARD_SETUP
#define CONFIG_CMD_BOOTZ
+#define CONFIG_MISC_INIT_R
+
+/* Hash command with SHA acceleration supported in hardware */
+#define CONFIG_CMD_HASH
+#define CONFIG_SHA_HW_ACCEL
+
#endif
--
1.8.1.4
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