On 09/15/2014 06:06 AM, Marek Vasut wrote:
> The timer reload value is a property of the timer hardware and there
> is no reason for this to be configurable. Place this into the timer
> driver just like on the other hardware.
> 
> Signed-off-by: Marek Vasut <ma...@denx.de>
> Cc: Chin Liang See <cl...@altera.com>
> Cc: Dinh Nguyen <dingu...@altera.com>
> Cc: Albert Aribaud <albert.u.b...@aribaud.net>
> Cc: Tom Rini <tr...@ti.com>
> Cc: Wolfgang Denk <w...@denx.de>
> Cc: Pavel Machek <pa...@denx.de>
> ---
>  arch/arm/cpu/armv7/socfpga/timer.c | 2 ++
>  include/configs/socfpga_cyclone5.h | 2 --
>  2 files changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm/cpu/armv7/socfpga/timer.c 
> b/arch/arm/cpu/armv7/socfpga/timer.c
> index 58fc789..253cde3 100644
> --- a/arch/arm/cpu/armv7/socfpga/timer.c
> +++ b/arch/arm/cpu/armv7/socfpga/timer.c
> @@ -8,6 +8,8 @@
>  #include <asm/io.h>
>  #include <asm/arch/timer.h>
>  
> +#define TIMER_LOAD_VAL               0xFFFFFFFF
> +
>  static const struct socfpga_timer *timer_base = (void *)CONFIG_SYS_TIMERBASE;
>  
>  /*
> diff --git a/include/configs/socfpga_cyclone5.h 
> b/include/configs/socfpga_cyclone5.h
> index 3b6cfb4..f50081b 100644
> --- a/include/configs/socfpga_cyclone5.h
> +++ b/include/configs/socfpga_cyclone5.h
> @@ -195,8 +195,6 @@
>  /* This timer use eosc1 where the clock frequency is fixed
>   * throughout any condition */
>  #define CONFIG_SYS_TIMERBASE         SOCFPGA_OSC1TIMER0_ADDRESS
> -/* reload value when timer count to zero */
> -#define TIMER_LOAD_VAL                       0xFFFFFFFF
>  /* Timer info */
>  #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
>  #define CONFIG_SYS_TIMER_RATE                2400000
> 

Acked-by: Dinh Nguyen <dingu...@opensource.altera.com>

Thanks...
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