Hi Stefan,
On 11/09/2014 15:07, Stefan Agner wrote:
> This adds initial support for Freescale NFC (NAND Flash Controller)
> found in ARM Vybrid SoC's, Power Architecture MPC5125 and others.
> The driver is called vf610_nfc since this is the first supported
> and tested hardware platform supported by the driver.
>
> Signed-off-by: Stefan Agner <ste...@agner.ch>
> ---
By applying I have seen some other minor issues. checkpatch reports some
warnings, can you fix them ?
WARNING: line over 80 characters
#200: FILE: drivers/mtd/nand/vf610_nfc.c:157:
+#define mtd_to_nfc(_mtd) (struct vf610_nfc *)((struct nand_chip
*)_mtd->priv)->priv;
CHECK: Alignment should match open parenthesis
#367: FILE: drivers/mtd/nand/vf610_nfc.c:324:
+ vf610_nfc_set_field(mtd, NFC_COL_ADDR, COL_ADDR_MASK,
+ COL_ADDR_SHIFT, column);
CHECK: Alignment should match open parenthesis
#371: FILE: drivers/mtd/nand/vf610_nfc.c:328:
+ vf610_nfc_set_field(mtd, NFC_ROW_ADDR, ROW_ADDR_MASK,
+ ROW_ADDR_SHIFT, page);
CHECK: Alignment should match open parenthesis
#388: FILE: drivers/mtd/nand/vf610_nfc.c:345:
+ vf610_nfc_send_commands(nfc->regs, NAND_CMD_SEQIN,
+ command, PROGRAM_PAGE_CMD_CODE);
CHECK: Alignment should match open parenthesis
#409: FILE: drivers/mtd/nand/vf610_nfc.c:366:
+ vf610_nfc_send_commands(nfc->regs, NAND_CMD_READ0,
+ NAND_CMD_READSTART, READ_PAGE_CMD_CODE);
CHECK: Alignment should match open parenthesis
#417: FILE: drivers/mtd/nand/vf610_nfc.c:374:
+ vf610_nfc_send_commands(nfc->regs, command,
+ NAND_CMD_ERASE2, ERASE_CMD_CODE);
WARNING: line over 80 characters
#428: FILE: drivers/mtd/nand/vf610_nfc.c:385:
+ vf610_nfc_send_command(nfc->regs, command,
STATUS_READ_CMD_CODE);
WARNING: line over 80 characters
#460: FILE: drivers/mtd/nand/vf610_nfc.c:417:
+ vf610_nfc_memcpy(buf, nfc->regs + NFC_MAIN_AREA(0) + c,
l);
CHECK: Alignment should match open parenthesis
#668: FILE: drivers/mtd/nand/vf610_nfc.c:625:
+ vf610_nfc_set_field(mtd, NFC_FLASH_CONFIG,
+ CONFIG_ECC_MODE_MASK,
CHECK: Alignment should match open parenthesis
#690: FILE: drivers/mtd/nand/vf610_nfc.c:647:
+ vf610_nfc_set_field(mtd, NFC_FLASH_CONFIG, CONFIG_PAGE_CNT_MASK,
+ CONFIG_PAGE_CNT_SHIFT, 1);
CHECK: Alignment should match open parenthesis
#694: FILE: drivers/mtd/nand/vf610_nfc.c:651:
+ vf610_nfc_set_field(mtd, NFC_FLASH_CONFIG,
+ CONFIG_ECC_SRAM_ADDR_MASK,
CHECK: Alignment should match open parenthesis
#737: FILE: drivers/mtd/nand/vf610_nfc.c:694:
+ vf610_nfc_set_field(mtd, NFC_FLASH_CONFIG,
+ CONFIG_ECC_MODE_MASK,
> drivers/mtd/nand/Makefile | 1 +
> drivers/mtd/nand/vf610_nfc.c | 721
> +++++++++++++++++++++++++++++++++++++++++++
> 2 files changed, 722 insertions(+)
> create mode 100644 drivers/mtd/nand/vf610_nfc.c
>
> diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
> index bf1312a..eef86d1 100644
> --- a/drivers/mtd/nand/Makefile
> +++ b/drivers/mtd/nand/Makefile
> @@ -51,6 +51,7 @@ obj-$(CONFIG_NAND_KB9202) += kb9202_nand.o
> obj-$(CONFIG_NAND_KIRKWOOD) += kirkwood_nand.o
> obj-$(CONFIG_NAND_KMETER1) += kmeter1_nand.o
> obj-$(CONFIG_NAND_MPC5121_NFC) += mpc5121_nfc.o
> +obj-$(CONFIG_NAND_VF610_NFC) += vf610_nfc.o
> obj-$(CONFIG_NAND_MXC) += mxc_nand.o
> obj-$(CONFIG_NAND_MXS) += mxs_nand.o
> obj-$(CONFIG_NAND_NDFC) += ndfc.o
> diff --git a/drivers/mtd/nand/vf610_nfc.c b/drivers/mtd/nand/vf610_nfc.c
> new file mode 100644
> index 0000000..f0eba9a
> --- /dev/null
> +++ b/drivers/mtd/nand/vf610_nfc.c
> @@ -0,0 +1,721 @@
> +/*
> + * Copyright 2009-2014 Freescale Semiconductor, Inc. and others
> + *
> + * Description: MPC5125, VF610, MCF54418 and Kinetis K70 Nand driver.
> + * Ported to U-Boot by Stefan Agner
> + * Based on RFC driver posted on Kernel Mailing list by Bill Pringlemeir
> + * Jason ported to M54418TWR and MVFA5.
> + * Authors: Stefan Agner <stefan.ag...@toradex.com>
> + * Bill Pringlemeir <bpringlem...@nbsps.com>
> + * Shaohui Xie <b21...@freescale.com>
> + * Jason Jin <jason....@freescale.com>
> + *
> + * Based on original driver mpc5121_nfc.c.
> + *
> + * This is free software; you can redistribute it and/or modify it
> + * under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * Limitations:
> + * - Untested on MPC5125 and M54418.
> + * - DMA not used.
> + * - 2K pages or less.
> + * - Only 2K page w. 64+OOB and hardware ECC.
> + */
> +
> +#include <common.h>
> +#include <malloc.h>
> +
> +#include <linux/mtd/mtd.h>
> +#include <linux/mtd/nand.h>
> +#include <linux/mtd/partitions.h>
> +
> +#include <nand.h>
> +#include <errno.h>
> +#include <asm/io.h>
> +
> +/* Register Offsets */
> +#define NFC_FLASH_CMD1 0x3F00
> +#define NFC_FLASH_CMD2 0x3F04
> +#define NFC_COL_ADDR 0x3F08
> +#define NFC_ROW_ADDR 0x3F0c
> +#define NFC_ROW_ADDR_INC 0x3F14
> +#define NFC_FLASH_STATUS1 0x3F18
> +#define NFC_FLASH_STATUS2 0x3F1c
> +#define NFC_CACHE_SWAP 0x3F28
> +#define NFC_SECTOR_SIZE 0x3F2c
> +#define NFC_FLASH_CONFIG 0x3F30
> +#define NFC_IRQ_STATUS 0x3F38
> +
> +/* Addresses for NFC MAIN RAM BUFFER areas */
> +#define NFC_MAIN_AREA(n) ((n) * 0x1000)
> +
> +#define PAGE_2K 0x0800
> +#define OOB_64 0x0040
> +
> +/*
> + * NFC_CMD2[CODE] values. See section:
> + * - 31.4.7 Flash Command Code Description, Vybrid manual
> + * - 23.8.6 Flash Command Sequencer, MPC5125 manual
> + *
> + * Briefly these are bitmasks of controller cycles.
> + */
> +#define READ_PAGE_CMD_CODE 0x7EE0
> +#define PROGRAM_PAGE_CMD_CODE 0x7FC0
> +#define ERASE_CMD_CODE 0x4EC0
> +#define READ_ID_CMD_CODE 0x4804
> +#define RESET_CMD_CODE 0x4040
> +#define STATUS_READ_CMD_CODE 0x4068
> +
> +/* NFC ECC mode define */
> +#define ECC_BYPASS 0
> +#define ECC_45_BYTE 6
> +
> +/*** Register Mask and bit definitions */
> +
> +/* NFC_FLASH_CMD1 Field */
> +#define CMD_BYTE2_MASK 0xFF000000
> +#define CMD_BYTE2_SHIFT 24
> +
> +/* NFC_FLASH_CM2 Field */
> +#define CMD_BYTE1_MASK 0xFF000000
> +#define CMD_BYTE1_SHIFT 24
> +#define CMD_CODE_MASK 0x00FFFF00
> +#define CMD_CODE_SHIFT 8
> +#define BUFNO_MASK 0x00000006
> +#define BUFNO_SHIFT 1
> +#define START_BIT (1<<0)
> +
> +/* NFC_COL_ADDR Field */
> +#define COL_ADDR_MASK 0x0000FFFF
> +#define COL_ADDR_SHIFT 0
> +
> +/* NFC_ROW_ADDR Field */
> +#define ROW_ADDR_MASK 0x00FFFFFF
> +#define ROW_ADDR_SHIFT 0
> +#define ROW_ADDR_CHIP_SEL_RB_MASK 0xF0000000
> +#define ROW_ADDR_CHIP_SEL_RB_SHIFT 28
> +#define ROW_ADDR_CHIP_SEL_MASK 0x0F000000
> +#define ROW_ADDR_CHIP_SEL_SHIFT 24
> +
> +/* NFC_FLASH_STATUS2 Field */
> +#define STATUS_BYTE1_MASK 0x000000FF
> +
> +/* NFC_FLASH_CONFIG Field */
> +#define CONFIG_ECC_SRAM_ADDR_MASK 0x7FC00000
> +#define CONFIG_ECC_SRAM_ADDR_SHIFT 22
> +#define CONFIG_ECC_SRAM_REQ_BIT (1<<21)
> +#define CONFIG_DMA_REQ_BIT (1<<20)
> +#define CONFIG_ECC_MODE_MASK 0x000E0000
> +#define CONFIG_ECC_MODE_SHIFT 17
> +#define CONFIG_FAST_FLASH_BIT (1<<16)
> +#define CONFIG_16BIT (1<<7)
> +#define CONFIG_BOOT_MODE_BIT (1<<6)
> +#define CONFIG_ADDR_AUTO_INCR_BIT (1<<5)
> +#define CONFIG_BUFNO_AUTO_INCR_BIT (1<<4)
> +#define CONFIG_PAGE_CNT_MASK 0xF
> +#define CONFIG_PAGE_CNT_SHIFT 0
> +
> +/* NFC_IRQ_STATUS Field */
> +#define IDLE_IRQ_BIT (1<<29)
> +#define IDLE_EN_BIT (1<<20)
> +#define CMD_DONE_CLEAR_BIT (1<<18)
> +#define IDLE_CLEAR_BIT (1<<17)
> +
> +#define NFC_TIMEOUT (1000)
> +
> +/* ECC status placed at end of buffers. */
> +#define ECC_SRAM_ADDR ((PAGE_2K+256-8) >> 3)
> +#define ECC_STATUS_MASK 0x80
> +#define ECC_ERR_COUNT 0x3F
> +
> +/*
> + * ECC status is stored at NFC_CFG[ECCADD] +4 for little-endian
> + * and +7 for big-endian SOC.
> + */
> +#ifdef CONFIG_VF610
> +#define ECC_OFFSET 4
> +#else
> +#define ECC_OFFSET 7
> +#endif
> +
> +struct vf610_nfc {
> + struct mtd_info *mtd;
> + struct nand_chip chip;
> + void __iomem *regs;
> + uint column;
> + int spareonly;
> + int page;
> + /* Status and ID are in alternate locations. */
> + int alt_buf;
> +#define ALT_BUF_ID 1
> +#define ALT_BUF_STAT 2
> + struct clk *clk;
> +};
> +
> +#define mtd_to_nfc(_mtd) (struct vf610_nfc *)((struct nand_chip
> *)_mtd->priv)->priv;
The ending semicolon should be not part of the macro.
Best regards,
Stefano Babic
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