This change detects the boot configuration of an OMAP3 device,
and uses that information on OMAP3 EVM builds to support
NAND or OneNAND.
Signed-off-by: Josh Karabin <gkara...@vocollect.com>
---
board/omap3/evm/evm.c | 24 +++++++++++
board/omap3/evm/evm.h | 4 +-
cpu/arm_cortexa8/omap3/mem.c | 71 ++++++++++++++++++++------------
include/asm-arm/arch-omap3/sys_proto.h | 2 +-
include/configs/omap3_evm.h | 4 ++
5 files changed, 76 insertions(+), 29 deletions(-)
diff --git a/board/omap3/evm/evm.c b/board/omap3/evm/evm.c
index c008c2e..e30e83f 100644
--- a/board/omap3/evm/evm.c
+++ b/board/omap3/evm/evm.c
@@ -34,6 +34,8 @@
#include <asm/arch/sys_proto.h>
#include <i2c.h>
#include <asm/mach-types.h>
+#include <environment.h>
+#include <command.h>
#include "evm.h"
/*
@@ -43,8 +45,30 @@
int board_init(void)
{
DECLARE_GLOBAL_DATA_PTR;
+#if defined(CONFIG_ENV_IS_IN_ONENAND) && defined(CONFIG_ENV_IS_IN_NAND)
+ int flash_type;
+ cmd_tbl_t *cmdtp;
+ flash_type = gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
+
+ switch (flash_type) {
+ case PISMO1_NAND:
+ env_object_ptr = &env_object_nand;
+ onenand_disable_init();
+ cmdtp = find_cmd("onenand");
+ cmdtp->name = NULL;
+ break;
+ case PISMO1_ONENAND:
+ env_object_ptr = &env_object_onenand;
+ nand_disable_init();
+ cmdtp = find_cmd("nand");
+ cmdtp->name = NULL;
+ break;
+ }
+#else
gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
+#endif
+
/* board id for Linux */
gd->bd->bi_arch_number = MACH_TYPE_OMAP3EVM;
/* boot param addr */
diff --git a/board/omap3/evm/evm.h b/board/omap3/evm/evm.h
index 4a82a7f..938cdbf 100644
--- a/board/omap3/evm/evm.h
+++ b/board/omap3/evm/evm.h
@@ -26,7 +26,9 @@
const omap3_sysinfo sysinfo = {
DDR_DISCRETE,
"OMAP3 EVM board",
-#if defined(CONFIG_ENV_IS_IN_ONENAND)
+#if defined(CONFIG_ENV_IS_IN_ONENAND) && defined(CONFIG_ENV_IS_IN_NAND)
+ "OneNAND or NAND"
+#elif defined(CONFIG_ENV_IS_IN_ONENAND)
"OneNAND",
#else
"NAND",
diff --git a/cpu/arm_cortexa8/omap3/mem.c b/cpu/arm_cortexa8/omap3/mem.c
index 3cc22c4..004088d 100644
--- a/cpu/arm_cortexa8/omap3/mem.c
+++ b/cpu/arm_cortexa8/omap3/mem.c
@@ -30,6 +30,8 @@
#include <asm/arch/mem.h>
#include <asm/arch/sys_proto.h>
#include <command.h>
+#include <onenand_uboot.h>
+#include <nand.h>
/*
* Only One NAND allowed on board at a time.
@@ -218,7 +220,7 @@ void enable_gpmc_config(u32 *gpmc_config, gpmc_csx_t
*gpmc_cs_base, u32 base,
* Init GPMC for x16, MuxMode (SDRAM in x32).
* This code can only be executed from SRAM or SDRAM.
*****************************************************/
-void gpmc_init(void)
+u32 gpmc_init(void)
{
/* putting a blanket check on GPMC based on ZeBu for now */
u32 *gpmc_config = NULL;
@@ -229,6 +231,7 @@ void gpmc_init(void)
u32 f_off = CONFIG_SYS_MONITOR_LEN;
u32 f_sec = 0;
u32 config = 0;
+ u32 b_type = 0;
/* global settings */
writel(0, &gpmc_base->irqenable); /* isr's sources masked */
@@ -245,40 +248,54 @@ void gpmc_init(void)
writel(0, &gpmc_cs_base->config7);
sdelay(1000);
+#if defined(CONFIG_CMD_NAND) || defined(CONFIG_CMD_ONENAND)
+ b_type = get_boot_type();
+#endif
+
#if defined(CONFIG_CMD_NAND) /* CS 0 */
- gpmc_config = gpmc_m_nand;
- gpmc_cfg_base = gpmc_base;
- nand_cs_base = (gpmc_csx_t *)(GPMC_CONFIG_CS0_BASE +
+ if (b_type == 0x1 || b_type == 0xc || b_type == 0xf ||
+ b_type == 0x15 || b_type == 0x1b) {
+ gpmc_config = gpmc_m_nand;
+ gpmc_cfg_base = gpmc_base;
+ nand_cs_base = (gpmc_csx_t *)(GPMC_CONFIG_CS0_BASE +
(GPMC_CS * GPMC_CONFIG_WIDTH));
- base = PISMO1_NAND_BASE;
- size = PISMO1_NAND_SIZE;
- enable_gpmc_config(gpmc_config, nand_cs_base, base, size);
+ base = PISMO1_NAND_BASE;
+ size = PISMO1_NAND_SIZE;
+ enable_gpmc_config(gpmc_config, nand_cs_base, base, size);
#if defined(CONFIG_ENV_IS_IN_NAND)
- f_off = SMNAND_ENV_OFFSET;
- f_sec = SZ_128K;
- /* env setup */
- boot_flash_base = base;
- boot_flash_off = f_off;
- boot_flash_sec = f_sec;
- boot_flash_env_addr = f_off;
+ f_off = SMNAND_ENV_OFFSET;
+ f_sec = SZ_128K;
+ /* env setup */
+ boot_flash_base = base;
+ boot_flash_off = f_off;
+ boot_flash_sec = f_sec;
+ boot_flash_env_addr = f_off;
+
+ return PISMO1_NAND;
+ }
#endif
#endif
#if defined(CONFIG_CMD_ONENAND)
- gpmc_config = gpmc_onenand;
- onenand_cs_base = (gpmc_csx_t *)(GPMC_CONFIG_CS0_BASE +
- (GPMC_CS * GPMC_CONFIG_WIDTH));
- base = PISMO1_ONEN_BASE;
- size = PISMO1_ONEN_SIZE;
- enable_gpmc_config(gpmc_config, onenand_cs_base, base, size);
+ if (b_type == 0x0 || b_type == 0x2 || b_type == 0x4 || b_type == 0x10 ||
+ b_type == 0x16) {
+ gpmc_config = gpmc_onenand;
+ onenand_cs_base = (gpmc_csx_t *)(GPMC_CONFIG_CS0_BASE +
+ (GPMC_CS *
GPMC_CONFIG_WIDTH));
+ base = PISMO1_ONEN_BASE;
+ size = PISMO1_ONEN_SIZE;
+ enable_gpmc_config(gpmc_config, onenand_cs_base, base, size);
#if defined(CONFIG_ENV_IS_IN_ONENAND)
- f_off = ONENAND_ENV_OFFSET;
- f_sec = SZ_128K;
- /* env setup */
- boot_flash_base = base;
- boot_flash_off = f_off;
- boot_flash_sec = f_sec;
- boot_flash_env_addr = f_off;
+ f_off = ONENAND_ENV_OFFSET;
+ f_sec = SZ_128K;
+ /* env setup */
+ boot_flash_base = base;
+ boot_flash_off = f_off;
+ boot_flash_sec = f_sec;
+ boot_flash_env_addr = f_off;
+
+ return PISMO1_ONENAND;
+ }
#endif
#endif
}
diff --git a/include/asm-arm/arch-omap3/sys_proto.h
b/include/asm-arm/arch-omap3/sys_proto.h
index 7361d08..63fb98e 100644
--- a/include/asm-arm/arch-omap3/sys_proto.h
+++ b/include/asm-arm/arch-omap3/sys_proto.h
@@ -33,7 +33,7 @@ void per_clocks_enable(void);
void memif_init(void);
void sdrc_init(void);
void do_sdrc_init(u32, u32);
-void gpmc_init(void);
+u32 gpmc_init(void);
void watchdog_init(void);
void set_muxconf_regs(void);
diff --git a/include/configs/omap3_evm.h b/include/configs/omap3_evm.h
index e205c01..b649808 100644
--- a/include/configs/omap3_evm.h
+++ b/include/configs/omap3_evm.h
@@ -112,6 +112,7 @@
#define CONFIG_CMD_I2C /* I2C serial bus support */
#define CONFIG_CMD_MMC /* MMC support */
#define CONFIG_CMD_ONENAND /* ONENAND support */
+#define CONFIG_CMD_NAND /* NAND support */
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_PING
@@ -130,12 +131,14 @@
/*
* Board NAND Info.
*/
+#define CONFIG_NAND_OMAP_GPMC
#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
/* to access nand */
#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
/* to access */
/* nand at CS0 */
+#define GPMC_NAND_ECC_LP_x16_LAYOUT 1
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */
/* NAND devices */
@@ -262,6 +265,7 @@
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP
+#define CONFIG_ENV_IS_IN_NAND 1
#define CONFIG_ENV_IS_IN_ONENAND 1
#define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */
#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
--
1.6.0.6
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