From: Stephen Warren <swar...@nvidia.com>
This pinmux tables currently omit any configuration for PCIe clk_req,
wake, and rst pins, which in turn causes intermittent failures in
U-Boot's PCIe support. Import an updated version of the pinmux tables
which rectifies this.
Signed-off-by: Stephen Warren <swar...@nvidia.com>
---
board/nvidia/jetson-tk1/pinmux-config-jetson-tk1.h | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/board/nvidia/jetson-tk1/pinmux-config-jetson-tk1.h
b/board/nvidia/jetson-tk1/pinmux-config-jetson-tk1.h
index d338818a64eb..de4eb355982c 100644
--- a/board/nvidia/jetson-tk1/pinmux-config-jetson-tk1.h
+++ b/board/nvidia/jetson-tk1/pinmux-config-jetson-tk1.h
@@ -283,6 +283,11 @@ static const struct pmux_pingrp_config
jetson_tk1_pingrps[] = {
PINCFG(PCC2, DEFAULT, DOWN, NORMAL, INPUT,
DEFAULT, DEFAULT),
PINCFG(SDMMC4_CLK_PCC4, SDMMC4, NORMAL, NORMAL, INPUT,
DEFAULT, DEFAULT),
PINCFG(CLK2_REQ_PCC5, DEFAULT, NORMAL, NORMAL, OUTPUT,
DEFAULT, DEFAULT),
+ PINCFG(PEX_L0_RST_N_PDD1, PE0, NORMAL, NORMAL, OUTPUT,
DEFAULT, DEFAULT),
+ PINCFG(PEX_L0_CLKREQ_N_PDD2, PE0, UP, NORMAL, INPUT,
DEFAULT, DEFAULT),
+ PINCFG(PEX_WAKE_N_PDD3, PE, UP, NORMAL, INPUT,
DEFAULT, DEFAULT),
+ PINCFG(PEX_L1_RST_N_PDD5, PE1, NORMAL, NORMAL, OUTPUT,
DEFAULT, DEFAULT),
+ PINCFG(PEX_L1_CLKREQ_N_PDD6, PE1, UP, NORMAL, INPUT,
DEFAULT, DEFAULT),
PINCFG(CLK3_OUT_PEE0, EXTPERIPH3, NORMAL, NORMAL, OUTPUT,
DEFAULT, DEFAULT),
PINCFG(CLK3_REQ_PEE1, DEFAULT, NORMAL, NORMAL, OUTPUT,
DEFAULT, DEFAULT),
PINCFG(DAP_MCLK1_REQ_PEE2, SATA, NORMAL, NORMAL, OUTPUT,
DEFAULT, DEFAULT),
--
1.9.1
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