Hi Ye, On 20/08/2014 11:18, Ye.Li wrote: > From: "Ye.Li" <ye...@freescale.com> > > The Latency parameters of PL310 Tag RAM latency control register and > Data RAM Latency control register are set in L2 cache enable. And > setting these registers must have PL310 NOT enabled. > > But when using Plugin mode boot, the PL310 is enabled by bootrom. > The patch disables the PL310 before applying this setting. > > Signed-off-by: Ye.Li <ye...@freescale.com> > --- > arch/arm/cpu/armv7/mx6/soc.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c > index f20bdeb..cc2231a 100644 > --- a/arch/arm/cpu/armv7/mx6/soc.c > +++ b/arch/arm/cpu/armv7/mx6/soc.c > @@ -394,6 +394,9 @@ void v7_outer_cache_enable(void) > } > #endif > > + /* Must disable the L2 before changing the latency parameters */ > + clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); > + > writel(0x132, &pl310->pl310_tag_latency_ctrl); > writel(0x132, &pl310->pl310_data_latency_ctrl); >
Acked-by: Stefano Babic <sba...@denx.de> Best regards, Stefano Babic -- ===================================================================== DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de ===================================================================== _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
