[U-Boot] [PATCH 6/7] xes: Update Freescale clock code to work with 86xx processors

[Peter Tyser]

Signed-off-by: Peter Tyser <pty...@xes-inc.com>
---
 board/xes/common/Makefile                          |    3 ++-
 .../xes/common/{fsl_8572_clk.c => fsl_8xxx_clk.c}  |    8 ++++++++
 2 files changed, 10 insertions(+), 1 deletions(-)
 rename board/xes/common/{fsl_8572_clk.c => fsl_8xxx_clk.c} (86%)

diff --git a/board/xes/common/Makefile b/board/xes/common/Makefile
index 6aef6f4..d022831 100644
--- a/board/xes/common/Makefile
+++ b/board/xes/common/Makefile
@@ -30,7 +30,8 @@ endif
 LIB    = $(obj)lib$(VENDOR).a
 
 COBJS-$(CONFIG_FSL_PCI_INIT)   += fsl_8xxx_pci.o
-COBJS-$(CONFIG_MPC8572)                += fsl_8572_clk.o
+COBJS-$(CONFIG_MPC8572)                += fsl_8xxx_clk.o
+COBJS-$(CONFIG_MPC86xx)                += fsl_8xxx_clk.o
 COBJS-$(CONFIG_FSL_DDR2)       += fsl_8xxx_ddr.o
 COBJS-$(CONFIG_NAND_ACTL)      += actl_nand.o
 
diff --git a/board/xes/common/fsl_8572_clk.c b/board/xes/common/fsl_8xxx_clk.c
similarity index 86%
rename from board/xes/common/fsl_8572_clk.c
rename to board/xes/common/fsl_8xxx_clk.c
index f5df2da..0155670 100644
--- a/board/xes/common/fsl_8572_clk.c
+++ b/board/xes/common/fsl_8xxx_clk.c
@@ -27,7 +27,12 @@
  */
 unsigned long get_board_sys_clk(ulong dummy)
 {
+#if defined(CONFIG_MPC85xx)
        volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+#elif defined(CONFIG_MPC86xx)
+       immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
+       volatile ccsr_gur_t *gur = &immap->im_gur;
+#endif
        u32 gpporcr = gur->gpporcr;
 
        if (gpporcr & 0x10000)
@@ -36,8 +41,10 @@ unsigned long get_board_sys_clk(ulong dummy)
                return 50000000;
 }
 
+#ifdef CONFIG_MPC85xx
 /*
  * Return DDR input clock - synchronous with SYSCLK or 66 MHz
+ * Note: 86xx doesn't support asynchronous DDR clk
  */
 unsigned long get_board_ddr_clk(ulong dummy)
 {
@@ -49,3 +56,4 @@ unsigned long get_board_ddr_clk(ulong dummy)
 
        return 66666666;
 }
+#endif
-- 
1.6.2.1

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