The Channel Start (CS) bit in the Mode Register (MR) should actually be
cleared as the comment in the code suggests. Previously, CS was being
set, not cleared.
Assuming normal operation of the DMA engine, this change shouldn't have
any real affect.
Signed-off-by: Peter Tyser <pty...@xes-inc.com>
---
drivers/dma/fsl_dma.c | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/drivers/dma/fsl_dma.c b/drivers/dma/fsl_dma.c
index 91a6d84..d41f04c 100644
--- a/drivers/dma/fsl_dma.c
+++ b/drivers/dma/fsl_dma.c
@@ -60,7 +60,7 @@ static uint dma_check(void) {
} while (status & FSL_DMA_SR_CB);
/* clear MR[CS] channel start bit */
- out_be32(&dma->mr, in_be32(&dma->mr) & FSL_DMA_MR_CS);
+ out_be32(&dma->mr, in_be32(&dma->mr) & ~FSL_DMA_MR_CS);
dma_sync();
if (status != 0)
--
1.6.2.1
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