Using CPU_HAS_PCR micro to present the SoC has pcr
(peripheral control register).
Signed-off-by: Bo Shen <voice.s...@atmel.com>
---
arch/arm/include/asm/arch-at91/at91_pmc.h | 2 +-
arch/arm/include/asm/arch-at91/sama5d3.h | 1 +
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/include/asm/arch-at91/at91_pmc.h
b/arch/arm/include/asm/arch-at91/at91_pmc.h
index bef5793..27331ff 100644
--- a/arch/arm/include/asm/arch-at91/at91_pmc.h
+++ b/arch/arm/include/asm/arch-at91/at91_pmc.h
@@ -54,7 +54,7 @@ typedef struct at91_pmc {
u32 reserved5[21];
u32 wpmr; /* 0xE4 Write Protect Mode Register (CAP0) */
u32 wpsr; /* 0xE8 Write Protect Status Register (CAP0) */
-#ifdef CONFIG_SAMA5D3
+#ifdef CPU_HAS_PCR
u32 reserved6[8];
u32 pcer1; /* 0x100 Periperial Clock Enable Register 1 */
u32 pcdr1; /* 0x104 Periperial Clock Disable Register 1 */
diff --git a/arch/arm/include/asm/arch-at91/sama5d3.h
b/arch/arm/include/asm/arch-at91/sama5d3.h
index 6d936f4..f7bc4ad 100644
--- a/arch/arm/include/asm/arch-at91/sama5d3.h
+++ b/arch/arm/include/asm/arch-at91/sama5d3.h
@@ -188,6 +188,7 @@
#define ATMEL_PIO_PORTS 5
#define CPU_HAS_PIO3
#define PIO_SCDR_DIV 0x3fff
+#define CPU_HAS_PCR
/*
* PMECC table in ROM
--
1.8.5.2
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