On Fri, Jun 27, 2014 at 01:31:14PM -0500, Cooper Jr., Franklin wrote: > From: "Franklin S. Cooper Jr" <fcoo...@ti.com> > > * Boot failures have been discovered due to a combination of routing issues > and > non optimal ddr3 timings in the EMIF > * Since ddr3 timings are different after significant board layout changes > different timings are required for alpha, beta and production boards. > > Signed-off-by: Franklin S. Cooper Jr <fcoo...@ti.com>
Applied to u-boot/master, thanks! -- Tom
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