On 06/26/2014 02:01 PM, Joakim Tjernlund wrote: ... > Strange, I had a look at the driver and I have a hard time figuring out > how/when START/STOP > is generated. However I don't think the current driver's > wait_for_transfer_complete() waits for > the START/STOP. I guess it waits until all data bytes are finished so STOP > completion time > isn't accounted for. > > Where is STOP initiated and where did you add the delay?
STOP (or REPEATED_START) happen automatically in HW once it's finished transferring all the bytes in the TX FIFO, and before the transaction complete interrupt is asserted. I added the delay immediately after the loop that spins waiting for "transaction complete" IRQ status to be set. _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
